209 lines
6.1 KiB
C
209 lines
6.1 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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/**
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* @file i2c_apll.h
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* @brief Register definitions for digital PLL (BBPLL)
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*
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* This file lists register fields of BBPLL, located on an internal configuration
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* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
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* rtc_clk_cpu_freq_set function in rtc_clk.c.
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*/
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#define I2C_BBPLL 0x66
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#define I2C_BBPLL_HOSTID 4
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#define I2C_BBPLL_IR_CAL_DELAY 0
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#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
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#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
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#define I2C_BBPLL_IR_CAL_CK_DIV 0
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#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
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#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
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#define I2C_BBPLL_IR_CAL_EXT_CAP 1
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#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
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#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
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#define I2C_BBPLL_IR_CAL_ENX_CAP 1
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#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
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#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
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#define I2C_BBPLL_IR_CAL_RSTB 1
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#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
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#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
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#define I2C_BBPLL_IR_CAL_START 1
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#define I2C_BBPLL_IR_CAL_START_MSB 6
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#define I2C_BBPLL_IR_CAL_START_LSB 6
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#define I2C_BBPLL_IR_CAL_UNSTOP 1
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#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
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#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
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#define I2C_BBPLL_OC_REF_DIV 2
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#define I2C_BBPLL_OC_REF_DIV_MSB 3
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#define I2C_BBPLL_OC_REF_DIV_LSB 0
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#define I2C_BBPLL_OC_DIV_10_8 2
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#define I2C_BBPLL_OC_DIV_10_8_MSB 6
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#define I2C_BBPLL_OC_DIV_10_8_LSB 4
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#define I2C_BBPLL_OC_LREF 2
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#define I2C_BBPLL_OC_LREF_MSB 7
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#define I2C_BBPLL_OC_LREF_LSB 7
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#define I2C_BBPLL_OC_DIV_7_0 3
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#define I2C_BBPLL_OC_DIV_7_0_MSB 7
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#define I2C_BBPLL_OC_DIV_7_0_LSB 0
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#define I2C_BBPLL_OC_ENB_FCAL 4
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#define I2C_BBPLL_OC_ENB_FCAL_MSB 0
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#define I2C_BBPLL_OC_ENB_FCAL_LSB 0
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#define I2C_BBPLL_OC_DCHGP 4
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#define I2C_BBPLL_OC_DCHGP_MSB 3
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#define I2C_BBPLL_OC_DCHGP_LSB 1
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#define I2C_BBPLL_OC_DHREF_SEL 4
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#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
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#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
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#define I2C_BBPLL_OC_DLREF_SEL 4
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#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
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#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
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#define I2C_BBPLL_OC_DCUR 5
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#define I2C_BBPLL_OC_DCUR_MSB 2
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#define I2C_BBPLL_OC_DCUR_LSB 0
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#define I2C_BBPLL_OC_BST_DIV 5
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#define I2C_BBPLL_OC_BST_DIV_MSB 3
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#define I2C_BBPLL_OC_BST_DIV_LSB 3
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#define I2C_BBPLL_OC_BST_E2C 5
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#define I2C_BBPLL_OC_BST_E2C_MSB 4
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#define I2C_BBPLL_OC_BST_E2C_LSB 4
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#define I2C_BBPLL_OC_TSCHGP 5
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#define I2C_BBPLL_OC_TSCHGP_MSB 5
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#define I2C_BBPLL_OC_TSCHGP_LSB 5
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#define I2C_BBPLL_OC_BW 5
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#define I2C_BBPLL_OC_BW_MSB 7
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#define I2C_BBPLL_OC_BW_LSB 6
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#define I2C_BBPLL_OR_LOCK1 6
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#define I2C_BBPLL_OR_LOCK1_MSB 0
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#define I2C_BBPLL_OR_LOCK1_LSB 0
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#define I2C_BBPLL_OR_LOCK2 6
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#define I2C_BBPLL_OR_LOCK2_MSB 1
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#define I2C_BBPLL_OR_LOCK2_LSB 1
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#define I2C_BBPLL_OR_CAL_CAP 7
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#define I2C_BBPLL_OR_CAL_CAP_MSB 3
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#define I2C_BBPLL_OR_CAL_CAP_LSB 0
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#define I2C_BBPLL_OR_CAL_UDF 7
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#define I2C_BBPLL_OR_CAL_UDF_MSB 4
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#define I2C_BBPLL_OR_CAL_UDF_LSB 4
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#define I2C_BBPLL_OR_CAL_OVF 7
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#define I2C_BBPLL_OR_CAL_OVF_MSB 5
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#define I2C_BBPLL_OR_CAL_OVF_LSB 5
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#define I2C_BBPLL_OR_CAL_END 7
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#define I2C_BBPLL_OR_CAL_END_MSB 6
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#define I2C_BBPLL_OR_CAL_END_LSB 6
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#define I2C_BBPLL_BBADC_DELAY1 8
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#define I2C_BBPLL_BBADC_DELAY1_MSB 1
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#define I2C_BBPLL_BBADC_DELAY1_LSB 0
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#define I2C_BBPLL_BBADC_DELAY2 8
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#define I2C_BBPLL_BBADC_DELAY2_MSB 3
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#define I2C_BBPLL_BBADC_DELAY2_LSB 2
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#define I2C_BBPLL_BBADC_DELAY3 8
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#define I2C_BBPLL_BBADC_DELAY3_MSB 5
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#define I2C_BBPLL_BBADC_DELAY3_LSB 4
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#define I2C_BBPLL_BBADC_DELAY4 8
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#define I2C_BBPLL_BBADC_DELAY4_MSB 7
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#define I2C_BBPLL_BBADC_DELAY4_LSB 6
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#define I2C_BBPLL_BBADC_DELAY5 9
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#define I2C_BBPLL_BBADC_DELAY5_MSB 1
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#define I2C_BBPLL_BBADC_DELAY5_LSB 0
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#define I2C_BBPLL_BBADC_DELAY6 9
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#define I2C_BBPLL_BBADC_DELAY6_MSB 3
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#define I2C_BBPLL_BBADC_DELAY6_LSB 2
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#define I2C_BBPLL_BBADC_DSMP 9
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#define I2C_BBPLL_BBADC_DSMP_MSB 7
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#define I2C_BBPLL_BBADC_DSMP_LSB 4
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#define I2C_BBPLL_DTEST 10
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#define I2C_BBPLL_DTEST_MSB 1
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#define I2C_BBPLL_DTEST_LSB 0
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#define I2C_BBPLL_ENT_ADC 10
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#define I2C_BBPLL_ENT_ADC_MSB 3
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#define I2C_BBPLL_ENT_ADC_LSB 2
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#define I2C_BBPLL_BBADC_DIV 10
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#define I2C_BBPLL_BBADC_DIV_MSB 5
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#define I2C_BBPLL_BBADC_DIV_LSB 4
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#define I2C_BBPLL_ENT_PLL 10
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#define I2C_BBPLL_ENT_PLL_MSB 6
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#define I2C_BBPLL_ENT_PLL_LSB 6
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#define I2C_BBPLL_OC_ENB_VCON 10
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#define I2C_BBPLL_OC_ENB_VCON_MSB 7
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#define I2C_BBPLL_OC_ENB_VCON_LSB 7
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#define I2C_BBPLL_DIV_DAC 11
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#define I2C_BBPLL_DIV_DAC_MSB 0
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#define I2C_BBPLL_DIV_DAC_LSB 0
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#define I2C_BBPLL_DIV_CPU 11
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#define I2C_BBPLL_DIV_CPU_MSB 1
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#define I2C_BBPLL_DIV_CPU_LSB 1
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#define I2C_BBPLL_BBADC_INPUT_SHORT 11
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#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
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#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
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#define I2C_BBPLL_BBADC_CAL_9_8 11
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#define I2C_BBPLL_BBADC_CAL_9_8_MSB 4
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#define I2C_BBPLL_BBADC_CAL_9_8_LSB 3
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#define I2C_BBPLL_BBADC_DCM 11
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#define I2C_BBPLL_BBADC_DCM_MSB 6
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#define I2C_BBPLL_BBADC_DCM_LSB 5
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#define I2C_BBPLL_ENDIV5 11
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#define I2C_BBPLL_ENDIV5_MSB 7
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#define I2C_BBPLL_ENDIV5_LSB 7
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#define I2C_BBPLL_BBADC_CAL_7_0 12
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#define I2C_BBPLL_BBADC_CAL_7_0_MSB 7
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#define I2C_BBPLL_BBADC_CAL_7_0_LSB 0
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