d3fde5188e
In case WiFi/BT stack has been enabled but wasn’t disabled, some RTC bits may be left enabled, causing increased current consumption. This change returns some of the bits back to their default values.
365 lines
13 KiB
C
365 lines
13 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stddef.h>
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#include <sys/lock.h>
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#include "esp_attr.h"
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#include "esp_deep_sleep.h"
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#include "esp_log.h"
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#include "rom/cache.h"
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#include "rom/rtc.h"
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#include "rom/uart.h"
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#include "soc/cpu.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "soc/dport_reg.h"
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#include "driver/rtc_io.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "rtc.h"
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#include "sdkconfig.h"
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/**
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* Internal structure which holds all requested deep sleep parameters
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*/
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typedef struct {
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esp_deep_sleep_pd_option_t pd_options[ESP_PD_DOMAIN_MAX];
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uint64_t sleep_duration;
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uint32_t wakeup_triggers : 11;
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uint32_t ext1_trigger_mode : 1;
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uint32_t ext1_rtc_gpio_mask : 18;
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uint32_t ext0_trigger_level : 1;
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uint32_t ext0_rtc_gpio_num : 5;
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} deep_sleep_config_t;
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static deep_sleep_config_t s_config = {
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.pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO },
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.wakeup_triggers = 0
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};
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/* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc()
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is not thread-safe. */
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static _lock_t lock_rtc_memory_crc;
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static const char* TAG = "deepsleep";
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static uint32_t get_power_down_flags();
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static void ext0_wakeup_prepare();
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static void ext1_wakeup_prepare();
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/* Wake from deep sleep stub
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See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
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*/
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esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
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{
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_lock_acquire(&lock_rtc_memory_crc);
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uint32_t stored_crc = REG_READ(RTC_MEMORY_CRC_REG);
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set_rtc_memory_crc();
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uint32_t calc_crc = REG_READ(RTC_MEMORY_CRC_REG);
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REG_WRITE(RTC_MEMORY_CRC_REG, stored_crc);
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_lock_release(&lock_rtc_memory_crc);
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if(stored_crc == calc_crc) {
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return (esp_deep_sleep_wake_stub_fn_t)REG_READ(RTC_ENTRY_ADDR_REG);
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} else {
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return NULL;
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}
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}
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void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
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{
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_lock_acquire(&lock_rtc_memory_crc);
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REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
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set_rtc_memory_crc();
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_lock_release(&lock_rtc_memory_crc);
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}
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void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) {
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/* Clear MMU for CPU 0 */
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REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR);
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REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MMU_IA_CLR);
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#if CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0
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// ROM code has not started yet, so we need to set delay factor
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// used by ets_delay_us first.
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ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000);
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// This delay is configured in menuconfig, it can be used to give
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// the flash chip some time to become ready.
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ets_delay_us(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY);
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#endif
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}
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void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
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void esp_deep_sleep(uint64_t time_in_us)
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{
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esp_deep_sleep_enable_timer_wakeup(time_in_us);
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esp_deep_sleep_start();
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}
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void IRAM_ATTR esp_deep_sleep_start()
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{
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// Decide which power domains can be powered down
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uint32_t pd_flags = get_power_down_flags();
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// Shut down parts of RTC which may have been left enabled by the wireless drivers
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
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RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
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RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_M, 0, SENS_FORCE_XPD_SAR_S);
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// Configure pins for external wakeup
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if (s_config.wakeup_triggers & EXT_EVENT0_TRIG_EN) {
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ext0_wakeup_prepare();
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}
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if (s_config.wakeup_triggers & EXT_EVENT1_TRIG_EN) {
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ext1_wakeup_prepare();
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}
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// TODO: move timer wakeup configuration into a similar function
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// once rtc_sleep is opensourced.
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// Flush UARTs so that output is not lost due to APB frequency change
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uart_tx_wait_idle(0);
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uart_tx_wait_idle(1);
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uart_tx_wait_idle(2);
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if (esp_get_deep_sleep_wake_stub() == NULL) {
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esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
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}
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rtc_set_cpu_freq(CPU_XTAL);
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uint32_t cycle_h = 0;
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uint32_t cycle_l = 0;
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// For timer wakeup, calibrate clock source against main XTAL
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// This is hardcoded to use 150kHz internal oscillator for now
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if (s_config.sleep_duration > 0) {
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uint32_t period = rtc_slowck_cali(CALI_RTC_MUX, 128);
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rtc_usec2rtc(s_config.sleep_duration >> 32, s_config.sleep_duration & UINT32_MAX,
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period, &cycle_h, &cycle_l);
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}
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// Enter deep sleep
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rtc_slp_prep_lite(pd_flags, 0);
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rtc_sleep(cycle_h, cycle_l, s_config.wakeup_triggers, 0);
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// Because RTC is in a slower clock domain than the CPU, it
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// can take several CPU cycles for the sleep mode to start.
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while (1) {
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;
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}
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}
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void system_deep_sleep(uint64_t) __attribute__((alias("esp_deep_sleep")));
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esp_err_t esp_deep_sleep_enable_ulp_wakeup()
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{
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#ifdef CONFIG_ULP_COPROC_ENABLED
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s_config.wakeup_triggers |= RTC_SAR_TRIG_EN;
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return ESP_OK;
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#else
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return ESP_ERR_INVALID_STATE;
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#endif
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}
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esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us)
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{
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s_config.wakeup_triggers |= RTC_TIMER_EXPIRE_EN;
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s_config.sleep_duration = time_in_us;
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return ESP_OK;
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}
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esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
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{
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if (level < 0 || level > 1) {
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return ESP_ERR_INVALID_ARG;
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}
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if (!RTC_GPIO_IS_VALID_GPIO(gpio_num)) {
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return ESP_ERR_INVALID_ARG;
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}
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s_config.ext0_rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
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s_config.ext0_trigger_level = level;
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s_config.wakeup_triggers |= RTC_EXT_EVENT0_TRIG_EN;
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return ESP_OK;
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}
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static void ext0_wakeup_prepare()
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{
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int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
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// Set GPIO to be used for wakeup
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REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtc_gpio_num);
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// Set level which will trigger wakeup
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SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
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s_config.ext0_trigger_level, RTC_CNTL_EXT_WAKEUP0_LV_S);
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// Find GPIO descriptor in the rtc_gpio_desc table and configure the pad
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for (size_t gpio_num = 0; gpio_num < GPIO_PIN_COUNT; ++gpio_num) {
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const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio_num];
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if (desc->rtc_num == rtc_gpio_num) {
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REG_SET_BIT(desc->reg, desc->mux);
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SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func);
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REG_SET_BIT(desc->reg, desc->slpsel);
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REG_SET_BIT(desc->reg, desc->slpie);
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break;
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}
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}
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}
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esp_err_t esp_deep_sleep_enable_ext1_wakeup(uint64_t mask, esp_ext1_wakeup_mode_t mode)
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{
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if (mode > ESP_EXT1_WAKEUP_ANY_HIGH) {
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return ESP_ERR_INVALID_ARG;
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}
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// Translate bit map of GPIO numbers into the bit map of RTC IO numbers
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uint32_t rtc_gpio_mask = 0;
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for (int gpio = 0; mask; ++gpio, mask >>= 1) {
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if ((mask & 1) == 0) {
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continue;
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}
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if (!RTC_GPIO_IS_VALID_GPIO(gpio)) {
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ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio);
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return ESP_ERR_INVALID_ARG;
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}
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rtc_gpio_mask |= BIT(rtc_gpio_desc[gpio].rtc_num);
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}
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s_config.ext1_rtc_gpio_mask = rtc_gpio_mask;
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s_config.ext1_trigger_mode = mode;
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s_config.wakeup_triggers |= RTC_EXT_EVENT1_TRIG_EN;
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return ESP_OK;
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}
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static void ext1_wakeup_prepare()
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{
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// Configure all RTC IOs selected as ext1 wakeup inputs
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uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
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for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
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int rtc_pin = rtc_gpio_desc[gpio].rtc_num;
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if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
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continue;
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}
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const rtc_gpio_desc_t* desc = &rtc_gpio_desc[gpio];
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// Route pad to RTC
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REG_SET_BIT(desc->reg, desc->mux);
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SET_PERI_REG_BITS(desc->reg, 0x3, 0, desc->func);
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// Pad configuration depends on RTC_PERIPH state in sleep mode
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if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_ON) {
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// set input enable in sleep mode
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REG_SET_BIT(desc->reg, desc->slpie);
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// allow sleep status signal to control IE/SLPIE mux
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REG_SET_BIT(desc->reg, desc->slpsel);
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} else {
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// RTC_PERIPH will be disabled, so need to enable input and
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// lock pad configuration. Pullups/pulldowns also need to be disabled.
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REG_SET_BIT(desc->reg, desc->ie);
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REG_CLR_BIT(desc->reg, desc->pulldown);
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REG_CLR_BIT(desc->reg, desc->pullup);
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REG_SET_BIT(RTC_CNTL_HOLD_FORCE_REG, desc->hold);
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}
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// Keep track of pins which are processed to bail out early
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rtc_gpio_mask &= ~BIT(rtc_pin);
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}
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// Clear state from previous wakeup
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REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
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// Set pins to be used for wakeup
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REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, s_config.ext1_rtc_gpio_mask);
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// Set logic function (any low, all high)
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SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1,
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s_config.ext1_trigger_mode, RTC_CNTL_EXT_WAKEUP1_LV_S);
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}
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uint64_t esp_deep_sleep_get_ext1_wakeup_status()
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{
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int wakeup_reason = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
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if (wakeup_reason != RTC_EXT_EVENT1_TRIG) {
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return 0;
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}
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uint32_t status = REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS);
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// Translate bit map of RTC IO numbers into the bit map of GPIO numbers
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uint64_t gpio_mask = 0;
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for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
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if (!RTC_GPIO_IS_VALID_GPIO(gpio)) {
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continue;
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}
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int rtc_pin = rtc_gpio_desc[gpio].rtc_num;
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if ((status & BIT(rtc_pin)) == 0) {
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continue;
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}
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gpio_mask |= BIT(gpio);
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}
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return gpio_mask;
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}
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esp_err_t esp_deep_sleep_pd_config(esp_deep_sleep_pd_domain_t domain,
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esp_deep_sleep_pd_option_t option)
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{
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if (domain >= ESP_PD_DOMAIN_MAX || option > ESP_PD_OPTION_AUTO) {
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return ESP_ERR_INVALID_ARG;
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}
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s_config.pd_options[domain] = option;
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return ESP_OK;
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}
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static uint32_t get_power_down_flags()
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{
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// Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.
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// RTC_SLOW_MEM is needed for the ULP, so keep RTC_SLOW_MEM powered up if ULP
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// is used and RTC_SLOW_MEM is Auto.
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// If there is any data placed into .rtc.data or .rtc.bss segments, and
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// RTC_SLOW_MEM is Auto, keep it powered up as well.
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// These labels are defined in the linker script:
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extern int _rtc_data_start, _rtc_data_end, _rtc_bss_start, _rtc_bss_end;
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if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] == ESP_PD_OPTION_AUTO ||
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&_rtc_data_end > &_rtc_data_start ||
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&_rtc_bss_end > &_rtc_bss_start) {
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s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] = ESP_PD_OPTION_ON;
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}
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// RTC_FAST_MEM is needed for deep sleep stub.
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// If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub
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// can run.
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// In the new chip revision, deep sleep stub will be optional,
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// and this can be changed.
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if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO) {
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s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
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}
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// RTC_PERIPH is needed for EXT0 wakeup and for ULP.
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// If RTC_PERIPH is auto, and both EXT0 and ULP aren't enabled,
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// power down RTC_PERIPH.
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if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) {
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if (s_config.wakeup_triggers &
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(RTC_SAR_TRIG_EN | RTC_EXT_EVENT0_TRIG_EN)) {
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s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
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}
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}
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const char* option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
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ESP_LOGD(TAG, "RTC_PERIPH: %s, RTC_SLOW_MEM: %s, RTC_FAST_MEM: %s",
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option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]],
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option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]],
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option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]);
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// Prepare flags based on the selected options
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uint32_t pd_flags = DEEP_SLEEP_PD_NORMAL;
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if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) {
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pd_flags |= DEEP_SLEEP_PD_RTC_FAST_MEM;
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}
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if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) {
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pd_flags |= DEEP_SLEEP_PD_RTC_SLOW_MEM;
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}
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if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
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pd_flags |= DEEP_SLEEP_PD_RTC_PERIPH;
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}
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return pd_flags;
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}
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