Using xxx_periph.h in whole IDF instead of xxx_reg.h, xxx_struct.h, xxx_channel.h ... . Cleaned up header files from unnecessary headers (releated to soc/... headers).
400 lines
12 KiB
C
400 lines
12 KiB
C
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "esp_system.h"
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#include "esp_attr.h"
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#include "esp_wifi.h"
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#include "esp_private/wifi.h"
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#include "esp_log.h"
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#include "sdkconfig.h"
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#include "esp32/rom/efuse.h"
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#include "esp32/rom/cache.h"
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#include "esp32/rom/uart.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_periph.h"
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#include "soc/efuse_periph.h"
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#include "soc/rtc_periph.h"
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#include "soc/timer_periph.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "soc/rtc_wdt.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/xtensa_api.h"
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#include "esp_heap_caps.h"
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#include "esp_private/system_internal.h"
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#include "esp_efuse.h"
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#include "esp_efuse_table.h"
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static const char* TAG = "system_api";
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static uint8_t base_mac_addr[6] = { 0 };
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#define SHUTDOWN_HANDLERS_NO 2
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static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
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void system_init()
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{
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}
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esp_err_t esp_base_mac_addr_set(uint8_t *mac)
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{
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if (mac == NULL) {
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ESP_LOGE(TAG, "Base MAC address is NULL");
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abort();
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}
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memcpy(base_mac_addr, mac, 6);
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return ESP_OK;
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}
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esp_err_t esp_base_mac_addr_get(uint8_t *mac)
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{
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uint8_t null_mac[6] = {0};
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if (memcmp(base_mac_addr, null_mac, 6) == 0) {
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ESP_LOGI(TAG, "Base MAC address is not set, read default base MAC address from BLK0 of EFUSE");
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return ESP_ERR_INVALID_MAC;
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}
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memcpy(mac, base_mac_addr, 6);
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return ESP_OK;
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}
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esp_err_t esp_efuse_mac_get_custom(uint8_t *mac)
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{
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uint8_t version;
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esp_efuse_read_field_blob(ESP_EFUSE_MAC_CUSTOM_VER, &version, 8);
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if (version != 1) {
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ESP_LOGE(TAG, "Base MAC address from BLK3 of EFUSE version error, version = %d", version);
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return ESP_ERR_INVALID_VERSION;
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}
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uint8_t efuse_crc;
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esp_efuse_read_field_blob(ESP_EFUSE_MAC_CUSTOM, mac, 48);
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esp_efuse_read_field_blob(ESP_EFUSE_MAC_CUSTOM_CRC, &efuse_crc, 8);
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uint8_t calc_crc = esp_crc8(mac, 6);
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if (efuse_crc != calc_crc) {
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ESP_LOGE(TAG, "Base MAC address from BLK3 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
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return ESP_ERR_INVALID_CRC;
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}
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return ESP_OK;
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}
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esp_err_t esp_efuse_mac_get_default(uint8_t* mac)
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{
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uint8_t efuse_crc;
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esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY, mac, 48);
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esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY_CRC, &efuse_crc, 8);
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uint8_t calc_crc = esp_crc8(mac, 6);
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if (efuse_crc != calc_crc) {
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// Small range of MAC addresses are accepted even if CRC is invalid.
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// These addresses are reserved for Espressif internal use.
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uint32_t mac_high = ((uint32_t)mac[0] << 8) | mac[1];
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if ((mac_high & 0xFFFF) == 0x18fe) {
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uint32_t mac_low = ((uint32_t)mac[2] << 24) | ((uint32_t)mac[3] << 16) | ((uint32_t)mac[4] << 8) | mac[5];
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if ((mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) {
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return ESP_OK;
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}
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} else {
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ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
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abort();
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}
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}
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return ESP_OK;
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}
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esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__((alias("esp_efuse_mac_get_default")));
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esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__((alias("esp_efuse_mac_get_default")));
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esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac)
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{
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uint8_t idx;
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if (local_mac == NULL || universal_mac == NULL) {
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ESP_LOGE(TAG, "mac address param is NULL");
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return ESP_ERR_INVALID_ARG;
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}
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memcpy(local_mac, universal_mac, 6);
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for (idx = 0; idx < 64; idx++) {
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local_mac[0] = universal_mac[0] | 0x02;
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local_mac[0] ^= idx << 2;
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if (memcmp(local_mac, universal_mac, 6)) {
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break;
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}
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}
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return ESP_OK;
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}
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esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type)
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{
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uint8_t efuse_mac[6];
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if (mac == NULL) {
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ESP_LOGE(TAG, "mac address param is NULL");
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return ESP_ERR_INVALID_ARG;
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}
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if (type < ESP_MAC_WIFI_STA || type > ESP_MAC_ETH) {
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ESP_LOGE(TAG, "mac type is incorrect");
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return ESP_ERR_INVALID_ARG;
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}
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_Static_assert(UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR \
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|| UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR, \
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"incorrect NUM_MAC_ADDRESS_FROM_EFUSE value");
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if (esp_base_mac_addr_get(efuse_mac) != ESP_OK) {
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esp_efuse_mac_get_default(efuse_mac);
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}
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switch (type) {
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case ESP_MAC_WIFI_STA:
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memcpy(mac, efuse_mac, 6);
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break;
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case ESP_MAC_WIFI_SOFTAP:
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if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
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memcpy(mac, efuse_mac, 6);
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mac[5] += 1;
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}
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else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
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esp_derive_local_mac(mac, efuse_mac);
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}
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break;
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case ESP_MAC_BT:
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memcpy(mac, efuse_mac, 6);
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if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
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mac[5] += 2;
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}
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else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
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mac[5] += 1;
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}
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break;
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case ESP_MAC_ETH:
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if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) {
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memcpy(mac, efuse_mac, 6);
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mac[5] += 3;
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}
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else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) {
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efuse_mac[5] += 1;
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esp_derive_local_mac(mac, efuse_mac);
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}
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break;
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default:
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ESP_LOGW(TAG, "incorrect mac type");
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break;
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}
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return ESP_OK;
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}
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esp_err_t esp_register_shutdown_handler(shutdown_handler_t handler)
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{
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for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
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if (shutdown_handlers[i] == handler) {
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return ESP_ERR_INVALID_STATE;
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} else if (shutdown_handlers[i] == NULL) {
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shutdown_handlers[i] = handler;
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return ESP_OK;
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}
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}
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return ESP_ERR_NO_MEM;
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}
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esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
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{
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for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
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if (shutdown_handlers[i] == handler) {
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shutdown_handlers[i] = NULL;
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return ESP_OK;
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}
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}
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return ESP_ERR_INVALID_STATE;
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}
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void esp_restart_noos() __attribute__ ((noreturn));
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void IRAM_ATTR esp_restart(void)
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{
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int i;
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for (i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
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if (shutdown_handlers[i]) {
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shutdown_handlers[i]();
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}
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}
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// Disable scheduler on this core.
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vTaskSuspendAll();
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esp_restart_noos();
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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* core are already stopped. Stalls other core, resets hardware,
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* triggers restart.
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*/
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void IRAM_ATTR esp_restart_noos()
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{
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// Disable interrupts
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xt_ints_off(0xFFFFFFFF);
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// Enable RTC watchdog for 1 second
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rtc_wdt_protect_off();
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rtc_wdt_disable();
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rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_RTC);
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rtc_wdt_set_stage(RTC_WDT_STAGE1, RTC_WDT_STAGE_ACTION_RESET_SYSTEM);
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rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_200ns);
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rtc_wdt_set_length_of_reset_signal(RTC_WDT_CPU_RESET_SIG, RTC_WDT_LENGTH_200ns);
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rtc_wdt_set_time(RTC_WDT_STAGE0, 1000);
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rtc_wdt_flashboot_mode_enable();
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// Reset and stall the other CPU.
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// CPU must be reset before stalling, in case it was running a s32c1i
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// instruction. This would cause memory pool to be locked by arbiter
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// to the stalled CPU, preventing current CPU from accessing this pool.
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const uint32_t core_id = xPortGetCoreID();
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const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
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esp_cpu_reset(other_core_id);
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esp_cpu_stall(other_core_id);
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// Other core is now stalled, can access DPORT registers directly
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esp_dport_access_int_abort();
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// Disable TG0/TG1 watchdogs
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TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
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TIMERG0.wdt_config0.en = 0;
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TIMERG0.wdt_wprotect=0;
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TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
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TIMERG1.wdt_config0.en = 0;
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TIMERG1.wdt_wprotect=0;
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// Flush any data left in UART FIFOs
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uart_tx_wait_idle(0);
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uart_tx_wait_idle(1);
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uart_tx_wait_idle(2);
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// Disable cache
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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// 2nd stage bootloader reconfigures SPI flash signals.
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// Reset them to the defaults expected by ROM.
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
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DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
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DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
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DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
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DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
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DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
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DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
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// Reset timer/spi/uart
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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// Set CPU back to XTAL source, no PLL, same as hard reset
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rtc_clk_cpu_freq_set_xtal();
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// Clear entry point for APP CPU
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DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
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// Reset CPUs
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if (core_id == 0) {
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// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
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esp_cpu_reset(1);
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esp_cpu_reset(0);
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} else {
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// Running on APP CPU: need to reset PRO CPU and unstall it,
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// then reset APP CPU
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esp_cpu_reset(0);
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esp_cpu_unstall(0);
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esp_cpu_reset(1);
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}
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while(true) {
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;
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}
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}
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void system_restart(void) __attribute__((alias("esp_restart")));
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uint32_t esp_get_free_heap_size( void )
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{
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return heap_caps_get_free_size( MALLOC_CAP_DEFAULT );
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}
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uint32_t esp_get_minimum_free_heap_size( void )
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{
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return heap_caps_get_minimum_free_size( MALLOC_CAP_DEFAULT );
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}
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uint32_t system_get_free_heap_size(void) __attribute__((alias("esp_get_free_heap_size")));
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const char* system_get_sdk_version(void)
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{
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return "master";
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}
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const char* esp_get_idf_version(void)
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{
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return IDF_VER;
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}
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static void get_chip_info_esp32(esp_chip_info_t* out_info)
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{
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uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
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memset(out_info, 0, sizeof(*out_info));
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out_info->model = CHIP_ESP32;
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if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) {
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out_info->revision = 1;
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}
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if ((reg & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
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out_info->cores = 2;
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} else {
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out_info->cores = 1;
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}
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out_info->features = CHIP_FEATURE_WIFI_BGN;
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if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
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out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
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}
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int package = (reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S;
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if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
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package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
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package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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out_info->features |= CHIP_FEATURE_EMB_FLASH;
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}
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}
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void esp_chip_info(esp_chip_info_t* out_info)
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{
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// Only ESP32 is supported now, in the future call one of the
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// chip-specific functions based on sdkconfig choice
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return get_chip_info_esp32(out_info);
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}
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