6353bc40d7
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz function can be used instead to get an approximate RTC_SLOW_CLK frequency - Clock calibration is performed at startup. The value is saved and used for timekeeping and when entering deep sleep. - When using the 32k XTAL, startup code will wait for the oscillator to start up. This can be possibly optimized by starting a separate task to wait for oscillator startup, and performing clock switch in that task. - Fix a bug that 32k XTAL would be disabled in rtc_clk_init. - Fix a rounding error in rtc_clk_cal, which caused systematic frequency error. - Fix an overflow bug which caused rtc_clk_cal to timeout early if the slow_clk_cycles argument would exceed certain value - Improve 32k XTAL oscillator startup time by introducing bootstrapping code, which uses internal pullup/pulldown resistors on 32K_N/32K_P pins to set better initial conditions for the oscillator.
532 lines
17 KiB
C
532 lines
17 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <xtensa/config/core.h>
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#include "rom/rtc.h"
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#include "rom/uart.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/xtensa_api.h"
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#include "soc/uart_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timer_group_struct.h"
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#include "soc/timer_group_reg.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "esp_gdbstub.h"
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#include "esp_panic.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_core_dump.h"
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#include "esp_spi_flash.h"
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#include "esp_cache_err_int.h"
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#include "esp_app_trace.h"
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/*
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Panic handlers; these get called when an unhandled exception occurs or the assembly-level
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task switching / interrupt code runs into an unrecoverable error. The default task stack
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overflow handler and abort handler are also in here.
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*/
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/*
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Note: The linker script will put everything in this file in IRAM/DRAM, so it also works with flash cache disabled.
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*/
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#if !CONFIG_ESP32_PANIC_SILENT_REBOOT
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//printf may be broken, so we fix our own printing fns...
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static void panicPutChar(char c)
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{
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while (((READ_PERI_REG(UART_STATUS_REG(CONFIG_CONSOLE_UART_NUM)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT) >= 126) ;
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WRITE_PERI_REG(UART_FIFO_REG(CONFIG_CONSOLE_UART_NUM), c);
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}
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static void panicPutStr(const char *c)
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{
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int x = 0;
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while (c[x] != 0) {
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panicPutChar(c[x]);
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x++;
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}
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}
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static void panicPutHex(int a)
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{
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int x;
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int c;
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for (x = 0; x < 8; x++) {
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c = (a >> 28) & 0xf;
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if (c < 10) {
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panicPutChar('0' + c);
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} else {
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panicPutChar('a' + c - 10);
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}
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a <<= 4;
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}
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}
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static void panicPutDec(int a)
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{
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int n1, n2;
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n1 = a % 10;
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n2 = a / 10;
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if (n2 == 0) {
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panicPutChar(' ');
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} else {
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panicPutChar(n2 + '0');
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}
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panicPutChar(n1 + '0');
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}
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#else
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//No printing wanted. Stub out these functions.
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static void panicPutChar(char c) { }
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static void panicPutStr(const char *c) { }
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static void panicPutHex(int a) { }
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static void panicPutDec(int a) { }
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#endif
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void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )
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{
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panicPutStr("***ERROR*** A stack overflow in task ");
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panicPutStr((char *)pcTaskName);
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panicPutStr(" has been detected.\r\n");
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abort();
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}
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static bool abort_called;
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static __attribute__((noreturn)) inline void invoke_abort()
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{
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abort_called = true;
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#if CONFIG_ESP32_APPTRACE_ENABLE
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, ESP_APPTRACE_TRAX_BLOCK_SIZE*CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TRAX_THRESH/100, CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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while(1) {
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__asm__ ("break 0,0");
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*((int*) 0) = 0;
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}
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}
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void abort()
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{
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#if !CONFIG_ESP32_PANIC_SILENT_REBOOT
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ets_printf("abort() was called at PC 0x%08x on core %d\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID());
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#endif
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invoke_abort();
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}
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static const char *edesc[] = {
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"IllegalInstruction", "Syscall", "InstructionFetchError", "LoadStoreError",
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"Level1Interrupt", "Alloca", "IntegerDivideByZero", "PCValue",
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"Privileged", "LoadStoreAlignment", "res", "res",
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"InstrPDAddrError", "LoadStorePIFDataError", "InstrPIFAddrError", "LoadStorePIFAddrError",
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"InstTLBMiss", "InstTLBMultiHit", "InstFetchPrivilege", "res",
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"InstrFetchProhibited", "res", "res", "res",
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"LoadStoreTLBMiss", "LoadStoreTLBMultihit", "LoadStorePrivilege", "res",
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"LoadProhibited", "StoreProhibited", "res", "res",
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"Cp0Dis", "Cp1Dis", "Cp2Dis", "Cp3Dis",
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"Cp4Dis", "Cp5Dis", "Cp6Dis", "Cp7Dis"
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};
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static void commonErrorHandler(XtExcFrame *frame);
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//The fact that we've panic'ed probably means the other CPU is now running wild, possibly
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//messing up the serial output, so we stall it here.
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static void haltOtherCore()
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{
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esp_cpu_stall( xPortGetCoreID() == 0 ? 1 : 0 );
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}
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static void setFirstBreakpoint(uint32_t pc)
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{
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asm(
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"wsr.ibreaka0 %0\n" \
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"rsr.ibreakenable a3\n" \
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"movi a4,1\n" \
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"or a4, a4, a3\n" \
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"wsr.ibreakenable a4\n" \
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::"r"(pc):"a3", "a4");
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}
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void panicHandler(XtExcFrame *frame)
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{
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int core_id = xPortGetCoreID();
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//Please keep in sync with PANIC_RSN_* defines
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const char *reasons[] = {
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"Unknown reason",
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"Unhandled debug exception",
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"Double exception",
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"Unhandled kernel exception",
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"Coprocessor exception",
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"Interrupt wdt timeout on CPU0",
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"Interrupt wdt timeout on CPU1",
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"Cache disabled but cached memory region accessed",
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};
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const char *reason = reasons[0];
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//The panic reason is stored in the EXCCAUSE register.
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if (frame->exccause <= PANIC_RSN_MAX) {
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reason = reasons[frame->exccause];
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}
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if (frame->exccause == PANIC_RSN_CACHEERR && esp_cache_err_get_cpuid() != core_id) {
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// Cache error interrupt will be handled by the panic handler
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// on the other CPU.
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return;
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}
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haltOtherCore();
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panicPutStr("Guru Meditation Error: Core ");
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panicPutDec(core_id);
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panicPutStr(" panic'ed (");
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if (!abort_called) {
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panicPutStr(reason);
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panicPutStr(")\r\n");
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if (frame->exccause == PANIC_RSN_DEBUGEXCEPTION) {
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int debugRsn;
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asm("rsr.debugcause %0":"=r"(debugRsn));
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panicPutStr("Debug exception reason: ");
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if (debugRsn&XCHAL_DEBUGCAUSE_ICOUNT_MASK) panicPutStr("SingleStep ");
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if (debugRsn&XCHAL_DEBUGCAUSE_IBREAK_MASK) panicPutStr("HwBreakpoint ");
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if (debugRsn&XCHAL_DEBUGCAUSE_DBREAK_MASK) {
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//Unlike what the ISA manual says, this core seemingly distinguishes from a DBREAK
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//reason caused by watchdog 0 and one caused by watchdog 1 by setting bit 8 of the
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//debugcause if the cause is watchdog 1 and clearing it if it's watchdog 0.
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if (debugRsn&(1<<8)) {
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#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
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panicPutStr("Stack canary watchpoint triggered ");
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#else
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panicPutStr("Watchpoint 1 triggered ");
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#endif
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} else {
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panicPutStr("Watchpoint 0 triggered ");
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}
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}
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if (debugRsn&XCHAL_DEBUGCAUSE_BREAK_MASK) panicPutStr("BREAK instr ");
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if (debugRsn&XCHAL_DEBUGCAUSE_BREAKN_MASK) panicPutStr("BREAKN instr ");
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if (debugRsn&XCHAL_DEBUGCAUSE_DEBUGINT_MASK) panicPutStr("DebugIntr ");
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panicPutStr("\r\n");
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}
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} else {
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panicPutStr("abort)\r\n");
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}
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if (esp_cpu_in_ocd_debug_mode()) {
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#if CONFIG_ESP32_APPTRACE_ENABLE
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, ESP_APPTRACE_TRAX_BLOCK_SIZE*CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TRAX_THRESH/100, CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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setFirstBreakpoint(frame->pc);
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return;
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}
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commonErrorHandler(frame);
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}
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void xt_unhandled_exception(XtExcFrame *frame)
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{
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haltOtherCore();
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panicPutStr("Guru Meditation Error of type ");
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int exccause = frame->exccause;
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if (exccause < 40) {
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panicPutStr(edesc[exccause]);
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} else {
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panicPutStr("Unknown");
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}
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panicPutStr(" occurred on core ");
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panicPutDec(xPortGetCoreID());
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if (esp_cpu_in_ocd_debug_mode()) {
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panicPutStr(" at pc=");
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panicPutHex(frame->pc);
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panicPutStr(". Setting bp and returning..\r\n");
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#if CONFIG_ESP32_APPTRACE_ENABLE
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, ESP_APPTRACE_TRAX_BLOCK_SIZE*CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TRAX_THRESH/100, CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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#endif
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//Stick a hardware breakpoint on the address the handler returns to. This way, the OCD debugger
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//will kick in exactly at the context the error happened.
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setFirstBreakpoint(frame->pc);
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return;
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}
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panicPutStr(". Exception was unhandled.\r\n");
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commonErrorHandler(frame);
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}
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/*
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If watchdogs are enabled, the panic handler runs the risk of getting aborted pre-emptively because
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an overzealous watchdog decides to reset it. On the other hand, if we disable all watchdogs, we run
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the risk of somehow halting in the panic handler and not resetting. That is why this routine kills
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all watchdogs except the timer group 0 watchdog, and it reconfigures that to reset the chip after
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one second.
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*/
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static void reconfigureAllWdts()
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{
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TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
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TIMERG0.wdt_feed = 1;
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TIMERG0.wdt_config0.sys_reset_length = 7; //3.2uS
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TIMERG0.wdt_config0.cpu_reset_length = 7; //3.2uS
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TIMERG0.wdt_config0.stg0 = TIMG_WDT_STG_SEL_RESET_SYSTEM; //1st stage timeout: reset system
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TIMERG0.wdt_config1.clk_prescale = 80 * 500; //Prescaler: wdt counts in ticks of 0.5mS
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TIMERG0.wdt_config2 = 2000; //1 second before reset
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TIMERG0.wdt_config0.en = 1;
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TIMERG0.wdt_wprotect = 0;
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//Disable wdt 1
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TIMERG1.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
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TIMERG1.wdt_config0.en = 0;
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TIMERG1.wdt_wprotect = 0;
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}
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/*
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This disables all the watchdogs for when we call the gdbstub.
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*/
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static inline void disableAllWdts()
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{
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TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
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TIMERG0.wdt_config0.en = 0;
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TIMERG0.wdt_wprotect = 0;
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TIMERG1.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
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TIMERG1.wdt_config0.en = 0;
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TIMERG1.wdt_wprotect = 0;
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}
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static void esp_panic_wdt_start()
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{
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if (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN)) {
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return;
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}
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WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
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WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_SYS_RESET_LENGTH, 7);
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_CPU_RESET_LENGTH, 7);
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG0, RTC_WDT_STG_SEL_RESET_SYSTEM);
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// 64KB of core dump data (stacks of about 30 tasks) will produce ~85KB base64 data.
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// @ 115200 UART speed it will take more than 6 sec to print them out.
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WRITE_PERI_REG(RTC_CNTL_WDTCONFIG1_REG, rtc_clk_slow_freq_get_hz() * 7);
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REG_SET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN);
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WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
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}
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void esp_panic_wdt_stop()
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{
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WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
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WRITE_PERI_REG(RTC_CNTL_WDTFEED_REG, 1);
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REG_SET_FIELD(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_STG0, RTC_WDT_STG_SEL_OFF);
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REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN);
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WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
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}
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static void esp_panic_dig_reset() __attribute__((noreturn));
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static void esp_panic_dig_reset()
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{
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// make sure all the panic handler output is sent from UART FIFO
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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// switch to XTAL (otherwise we will keep running from the PLL)
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rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
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// reset the digital part
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esp_cpu_unstall(PRO_CPU_NUM);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
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while (true) {
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;
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}
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}
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static inline bool stackPointerIsSane(uint32_t sp)
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{
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return !(sp < 0x3ffae010 || sp > 0x3ffffff0 || ((sp & 0xf) != 0));
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}
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static void putEntry(uint32_t pc, uint32_t sp)
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{
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if (pc & 0x80000000) {
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pc = (pc & 0x3fffffff) | 0x40000000;
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}
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panicPutStr(" 0x");
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panicPutHex(pc);
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panicPutStr(":0x");
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panicPutHex(sp);
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}
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static void doBacktrace(XtExcFrame *frame)
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{
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uint32_t i = 0, pc = frame->pc, sp = frame->a1;
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panicPutStr("\r\nBacktrace:");
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/* Do not check sanity on first entry, PC could be smashed. */
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putEntry(pc, sp);
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pc = frame->a0;
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while (i++ < 100) {
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uint32_t psp = sp;
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if (!stackPointerIsSane(sp) || i++ > 100) {
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break;
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}
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sp = *((uint32_t *) (sp - 0x10 + 4));
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putEntry(pc, sp);
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pc = *((uint32_t *) (psp - 0x10));
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if (pc < 0x40000000) {
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break;
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}
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}
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panicPutStr("\r\n\r\n");
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}
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void esp_restart_noos() __attribute__ ((noreturn));
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/*
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We arrive here after a panic or unhandled exception, when no OCD is detected. Dump the registers to the
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serial port and either jump to the gdb stub, halt the CPU or reboot.
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*/
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static void commonErrorHandler(XtExcFrame *frame)
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{
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int *regs = (int *)frame;
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int x, y;
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const char *sdesc[] = {
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"PC ", "PS ", "A0 ", "A1 ", "A2 ", "A3 ", "A4 ", "A5 ",
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"A6 ", "A7 ", "A8 ", "A9 ", "A10 ", "A11 ", "A12 ", "A13 ",
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"A14 ", "A15 ", "SAR ", "EXCCAUSE", "EXCVADDR", "LBEG ", "LEND ", "LCOUNT "
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};
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// start panic WDT to restart system if we hang in this handler
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esp_panic_wdt_start();
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//Feed the watchdogs, so they will give us time to print out debug info
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reconfigureAllWdts();
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/* only dump registers for 'real' crashes, if crashing via abort()
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the register window is no longer useful.
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*/
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if (!abort_called) {
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panicPutStr("Register dump:\r\n");
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for (x = 0; x < 24; x += 4) {
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for (y = 0; y < 4; y++) {
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if (sdesc[x + y][0] != 0) {
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panicPutStr(sdesc[x + y]);
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panicPutStr(": 0x");
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panicPutHex(regs[x + y + 1]);
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panicPutStr(" ");
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}
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}
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panicPutStr("\r\n");
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}
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}
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/* With windowed ABI backtracing is easy, let's do it. */
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doBacktrace(frame);
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#if CONFIG_ESP32_APPTRACE_ENABLE
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disableAllWdts();
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esp_apptrace_flush_nolock(ESP_APPTRACE_DEST_TRAX, ESP_APPTRACE_TRAX_BLOCK_SIZE*CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TRAX_THRESH/100, CONFIG_ESP32_APPTRACE_ONPANIC_HOST_FLUSH_TMO);
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reconfigureAllWdts();
|
|
#endif
|
|
|
|
#if CONFIG_ESP32_PANIC_GDBSTUB
|
|
disableAllWdts();
|
|
esp_panic_wdt_stop();
|
|
panicPutStr("Entering gdb stub now.\r\n");
|
|
esp_gdbstub_panic_handler(frame);
|
|
#else
|
|
#if CONFIG_ESP32_ENABLE_COREDUMP
|
|
disableAllWdts();
|
|
#if CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH
|
|
esp_core_dump_to_flash(frame);
|
|
#endif
|
|
#if CONFIG_ESP32_ENABLE_COREDUMP_TO_UART && !CONFIG_ESP32_PANIC_SILENT_REBOOT
|
|
esp_core_dump_to_uart(frame);
|
|
#endif
|
|
reconfigureAllWdts();
|
|
#endif
|
|
esp_panic_wdt_stop();
|
|
#if CONFIG_ESP32_PANIC_PRINT_REBOOT || CONFIG_ESP32_PANIC_SILENT_REBOOT
|
|
panicPutStr("Rebooting...\r\n");
|
|
if (frame->exccause != PANIC_RSN_CACHEERR) {
|
|
esp_restart_noos();
|
|
} else {
|
|
// The only way to clear invalid cache access interrupt is to reset the digital part
|
|
esp_panic_dig_reset();
|
|
}
|
|
#else
|
|
disableAllWdts();
|
|
panicPutStr("CPU halted.\r\n");
|
|
while (1);
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
|
|
void esp_set_breakpoint_if_jtag(void *fn)
|
|
{
|
|
if (esp_cpu_in_ocd_debug_mode()) {
|
|
setFirstBreakpoint((uint32_t)fn);
|
|
}
|
|
}
|
|
|
|
|
|
esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags)
|
|
{
|
|
int x;
|
|
if (no<0 || no>1) return ESP_ERR_INVALID_ARG;
|
|
if (flags&(~0xC0000000)) return ESP_ERR_INVALID_ARG;
|
|
int dbreakc=0x3F;
|
|
//We support watching 2^n byte values, from 1 to 64. Calculate the mask for that.
|
|
for (x=0; x<7; x++) {
|
|
if (size==(1<<x)) break;
|
|
dbreakc<<=1;
|
|
}
|
|
if (x==7) return ESP_ERR_INVALID_ARG;
|
|
//Mask mask and add in flags.
|
|
dbreakc=(dbreakc&0x3f)|flags;
|
|
|
|
if (no==0) {
|
|
asm volatile(
|
|
"wsr.dbreaka0 %0\n" \
|
|
"wsr.dbreakc0 %1\n" \
|
|
::"r"(adr),"r"(dbreakc));
|
|
} else {
|
|
asm volatile(
|
|
"wsr.dbreaka1 %0\n" \
|
|
"wsr.dbreakc1 %1\n" \
|
|
::"r"(adr),"r"(dbreakc));
|
|
}
|
|
return ESP_OK;
|
|
}
|
|
|
|
void esp_clear_watchpoint(int no)
|
|
{
|
|
//Setting a dbreakc register to 0 makes it trigger on neither load nor store, effectively disabling it.
|
|
int dbreakc=0;
|
|
if (no==0) {
|
|
asm volatile(
|
|
"wsr.dbreakc0 %0\n" \
|
|
::"r"(dbreakc));
|
|
} else {
|
|
asm volatile(
|
|
"wsr.dbreakc1 %0\n" \
|
|
::"r"(dbreakc));
|
|
}
|
|
}
|
|
|
|
void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression)
|
|
{
|
|
ets_printf("ESP_ERROR_CHECK failed: esp_err_t 0x%x at 0x%08x\n", rc, (intptr_t)__builtin_return_address(0) - 3);
|
|
if (spi_flash_cache_enabled()) { // strings may be in flash cache
|
|
ets_printf("file: \"%s\" line %d\nfunc: %s\nexpression: %s\n", file, line, function, expression);
|
|
}
|
|
invoke_abort();
|
|
}
|