1. separate rom include files and linkscript to esp_rom 2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h" 3. Forward compatible 4. update mqtt
434 lines
15 KiB
C
434 lines
15 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <assert.h>
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#include <string.h>
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#include <stdio.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include <esp32/rom/spi_flash.h>
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#include <esp32/rom/cache.h>
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#include <soc/soc.h>
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#include <soc/dport_reg.h>
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#include "sdkconfig.h"
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#include "esp_ipc.h"
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#include "esp_attr.h"
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#include "esp_spi_flash.h"
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#include "esp_flash_encrypt.h"
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#include "esp_log.h"
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#include "cache_utils.h"
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#include "esp32/spiram.h"
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#ifndef NDEBUG
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// Enable built-in checks in queue.h in debug builds
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#define INVARIANTS
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#endif
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#include "sys/queue.h"
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#define REGIONS_COUNT 4
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#define PAGES_PER_REGION 64
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#define INVALID_ENTRY_VAL 0x100
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#define VADDR0_START_ADDR 0x3F400000
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#define VADDR1_START_ADDR 0x40000000
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#define VADDR1_FIRST_USABLE_ADDR 0x400D0000
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#define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + 64)
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typedef struct mmap_entry_{
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uint32_t handle;
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int page;
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int count;
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LIST_ENTRY(mmap_entry_) entries;
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} mmap_entry_t;
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static LIST_HEAD(mmap_entries_head, mmap_entry_) s_mmap_entries_head =
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LIST_HEAD_INITIALIZER(s_mmap_entries_head);
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static uint8_t s_mmap_page_refcnt[REGIONS_COUNT * PAGES_PER_REGION] = {0};
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static uint32_t s_mmap_last_handle = 0;
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static void IRAM_ATTR spi_flash_mmap_init()
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{
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if (s_mmap_page_refcnt[0] != 0) {
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return; /* mmap data already initialised */
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}
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DPORT_INTERRUPT_DISABLE();
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for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) {
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uint32_t entry_pro = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]);
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uint32_t entry_app = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[i]);
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if (entry_pro != entry_app) {
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// clean up entries used by boot loader
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entry_pro = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
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DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
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}
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if ((entry_pro & INVALID_ENTRY_VAL) == 0 && (i == 0 || i == PRO_IRAM0_FIRST_USABLE_PAGE || entry_pro != 0)) {
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s_mmap_page_refcnt[i] = 1;
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} else {
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DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
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DPORT_APP_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
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}
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}
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DPORT_INTERRUPT_RESTORE();
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}
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static void IRAM_ATTR get_mmu_region(spi_flash_mmap_memory_t memory, int* out_begin, int* out_size,uint32_t* region_addr)
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{
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if (memory == SPI_FLASH_MMAP_DATA) {
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// Vaddr0
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*out_begin = 0;
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*out_size = 64;
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*region_addr = VADDR0_START_ADDR;
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} else {
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// only part of VAddr1 is usable, so adjust for that
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*out_begin = PRO_IRAM0_FIRST_USABLE_PAGE;
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*out_size = 3 * 64 - *out_begin;
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*region_addr = VADDR1_FIRST_USABLE_ADDR;
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}
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}
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esp_err_t IRAM_ATTR spi_flash_mmap(size_t src_addr, size_t size, spi_flash_mmap_memory_t memory,
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const void** out_ptr, spi_flash_mmap_handle_t* out_handle)
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{
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esp_err_t ret;
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if (src_addr & 0xffff) {
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return ESP_ERR_INVALID_ARG;
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}
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if (src_addr + size > g_rom_flashchip.chip_size) {
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return ESP_ERR_INVALID_ARG;
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}
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// region which should be mapped
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int phys_page = src_addr / SPI_FLASH_MMU_PAGE_SIZE;
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int page_count = (size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE;
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// prepare a linear pages array to feed into spi_flash_mmap_pages
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int *pages = heap_caps_malloc(sizeof(int)*page_count, MALLOC_CAP_INTERNAL);
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if (pages == NULL) {
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return ESP_ERR_NO_MEM;
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}
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for (int i = 0; i < page_count; i++) {
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pages[i] = phys_page+i;
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}
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ret = spi_flash_mmap_pages(pages, page_count, memory, out_ptr, out_handle);
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free(pages);
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return ret;
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}
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esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, spi_flash_mmap_memory_t memory,
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const void** out_ptr, spi_flash_mmap_handle_t* out_handle)
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{
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esp_err_t ret;
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bool need_flush = false;
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if (!page_count) {
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return ESP_ERR_INVALID_ARG;
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}
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if (!esp_ptr_internal(pages)) {
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return ESP_ERR_INVALID_ARG;
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}
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for (int i = 0; i < page_count; i++) {
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if (pages[i] < 0 || pages[i]*SPI_FLASH_MMU_PAGE_SIZE >= g_rom_flashchip.chip_size) {
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return ESP_ERR_INVALID_ARG;
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}
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}
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mmap_entry_t* new_entry = (mmap_entry_t*) heap_caps_malloc(sizeof(mmap_entry_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
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if (new_entry == 0) {
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return ESP_ERR_NO_MEM;
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}
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spi_flash_disable_interrupts_caches_and_other_cpu();
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spi_flash_mmap_init();
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// figure out the memory region where we should look for pages
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int region_begin; // first page to check
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int region_size; // number of pages to check
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uint32_t region_addr; // base address of memory region
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get_mmu_region(memory,®ion_begin,®ion_size,®ion_addr);
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if (region_size < page_count) {
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return ESP_ERR_NO_MEM;
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}
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// The following part searches for a range of MMU entries which can be used.
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// Algorithm is essentially naïve strstr algorithm, except that unused MMU
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// entries are treated as wildcards.
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int start;
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// the " + 1" is a fix when loop the MMU table pages, because the last MMU page
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// is valid as well if it have not been used
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int end = region_begin + region_size - page_count + 1;
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for (start = region_begin; start < end; ++start) {
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int pageno = 0;
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int pos;
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DPORT_INTERRUPT_DISABLE();
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for (pos = start; pos < start + page_count; ++pos, ++pageno) {
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int table_val = (int) DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[pos]);
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uint8_t refcnt = s_mmap_page_refcnt[pos];
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if (refcnt != 0 && table_val != pages[pageno]) {
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break;
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}
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}
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DPORT_INTERRUPT_RESTORE();
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// whole mapping range matched, bail out
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if (pos - start == page_count) {
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break;
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}
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}
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// checked all the region(s) and haven't found anything?
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if (start == end) {
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*out_handle = 0;
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*out_ptr = NULL;
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ret = ESP_ERR_NO_MEM;
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} else {
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// set up mapping using pages
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uint32_t pageno = 0;
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DPORT_INTERRUPT_DISABLE();
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for (int i = start; i != start + page_count; ++i, ++pageno) {
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// sanity check: we won't reconfigure entries with non-zero reference count
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uint32_t entry_pro = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]);
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uint32_t entry_app = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[i]);
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assert(s_mmap_page_refcnt[i] == 0 ||
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(entry_pro == pages[pageno] &&
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entry_app == pages[pageno]));
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if (s_mmap_page_refcnt[i] == 0) {
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if (entry_pro != pages[pageno] || entry_app != pages[pageno]) {
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DPORT_PRO_FLASH_MMU_TABLE[i] = pages[pageno];
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DPORT_APP_FLASH_MMU_TABLE[i] = pages[pageno];
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need_flush = true;
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}
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}
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++s_mmap_page_refcnt[i];
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}
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DPORT_INTERRUPT_RESTORE();
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LIST_INSERT_HEAD(&s_mmap_entries_head, new_entry, entries);
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new_entry->page = start;
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new_entry->count = page_count;
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new_entry->handle = ++s_mmap_last_handle;
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*out_handle = new_entry->handle;
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*out_ptr = (void*) (region_addr + (start - region_begin) * SPI_FLASH_MMU_PAGE_SIZE);
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ret = ESP_OK;
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}
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/* This is a temporary fix for an issue where some
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cache reads may see stale data.
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Working on a long term fix that doesn't require invalidating
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entire cache.
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*/
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if (need_flush) {
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#if CONFIG_SPIRAM_SUPPORT
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esp_spiram_writeback_cache();
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#endif
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Cache_Flush(0);
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Cache_Flush(1);
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}
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spi_flash_enable_interrupts_caches_and_other_cpu();
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if (*out_ptr == NULL) {
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free(new_entry);
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}
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return ret;
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}
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void IRAM_ATTR spi_flash_munmap(spi_flash_mmap_handle_t handle)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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mmap_entry_t* it;
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// look for handle in linked list
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for (it = LIST_FIRST(&s_mmap_entries_head); it != NULL; it = LIST_NEXT(it, entries)) {
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if (it->handle == handle) {
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// for each page, decrement reference counter
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// if reference count is zero, disable MMU table entry to
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// facilitate debugging of use-after-free conditions
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for (int i = it->page; i < it->page + it->count; ++i) {
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assert(s_mmap_page_refcnt[i] > 0);
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if (--s_mmap_page_refcnt[i] == 0) {
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DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
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DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL;
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}
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}
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LIST_REMOVE(it, entries);
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break;
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}
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}
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spi_flash_enable_interrupts_caches_and_other_cpu();
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if (it == NULL) {
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assert(0 && "invalid handle, or handle already unmapped");
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}
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free(it);
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}
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static void IRAM_ATTR NOINLINE_ATTR spi_flash_protected_mmap_init()
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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spi_flash_mmap_init();
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spi_flash_enable_interrupts_caches_and_other_cpu();
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}
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static uint32_t IRAM_ATTR NOINLINE_ATTR spi_flash_protected_read_mmu_entry(int index)
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{
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uint32_t value;
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spi_flash_disable_interrupts_caches_and_other_cpu();
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value = DPORT_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[index]);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return value;
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}
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void spi_flash_mmap_dump()
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{
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spi_flash_protected_mmap_init();
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mmap_entry_t* it;
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for (it = LIST_FIRST(&s_mmap_entries_head); it != NULL; it = LIST_NEXT(it, entries)) {
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printf("handle=%d page=%d count=%d\n", it->handle, it->page, it->count);
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}
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for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) {
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if (s_mmap_page_refcnt[i] != 0) {
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uint32_t paddr = spi_flash_protected_read_mmu_entry(i);
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printf("page %d: refcnt=%d paddr=%d\n", i, (int) s_mmap_page_refcnt[i], paddr);
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}
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}
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}
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uint32_t IRAM_ATTR spi_flash_mmap_get_free_pages(spi_flash_mmap_memory_t memory)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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spi_flash_mmap_init();
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int count = 0;
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int region_begin; // first page to check
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int region_size; // number of pages to check
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uint32_t region_addr; // base address of memory region
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get_mmu_region(memory,®ion_begin,®ion_size,®ion_addr);
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DPORT_INTERRUPT_DISABLE();
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for (int i = region_begin; i < region_begin + region_size; ++i) {
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if (s_mmap_page_refcnt[i] == 0 && DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]) == INVALID_ENTRY_VAL) {
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count++;
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}
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}
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DPORT_INTERRUPT_RESTORE();
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return count;
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}
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uint32_t spi_flash_cache2phys(const void *cached)
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{
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intptr_t c = (intptr_t)cached;
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size_t cache_page;
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if (c >= VADDR1_START_ADDR && c < VADDR1_FIRST_USABLE_ADDR) {
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/* IRAM address, doesn't map to flash */
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return SPI_FLASH_CACHE2PHYS_FAIL;
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}
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else if (c < VADDR1_FIRST_USABLE_ADDR) {
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/* expect cache is in DROM */
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cache_page = (c - VADDR0_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE;
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} else {
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/* expect cache is in IROM */
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cache_page = (c - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + 64;
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}
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if (cache_page >= 256) {
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/* cached address was not in IROM or DROM */
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return SPI_FLASH_CACHE2PHYS_FAIL;
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}
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uint32_t phys_page = spi_flash_protected_read_mmu_entry(cache_page);
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if (phys_page == INVALID_ENTRY_VAL) {
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/* page is not mapped */
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return SPI_FLASH_CACHE2PHYS_FAIL;
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}
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uint32_t phys_offs = phys_page * SPI_FLASH_MMU_PAGE_SIZE;
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return phys_offs | (c & (SPI_FLASH_MMU_PAGE_SIZE-1));
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}
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const void *IRAM_ATTR spi_flash_phys2cache(uint32_t phys_offs, spi_flash_mmap_memory_t memory)
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{
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uint32_t phys_page = phys_offs / SPI_FLASH_MMU_PAGE_SIZE;
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int start, end, page_delta;
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intptr_t base;
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if (memory == SPI_FLASH_MMAP_DATA) {
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start = 0;
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end = 64;
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base = VADDR0_START_ADDR;
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page_delta = 0;
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} else {
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start = PRO_IRAM0_FIRST_USABLE_PAGE;
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end = 256;
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base = VADDR1_START_ADDR;
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page_delta = 64;
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}
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spi_flash_disable_interrupts_caches_and_other_cpu();
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DPORT_INTERRUPT_DISABLE();
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for (int i = start; i < end; i++) {
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if (DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]) == phys_page) {
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i -= page_delta;
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intptr_t cache_page = base + (SPI_FLASH_MMU_PAGE_SIZE * i);
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DPORT_INTERRUPT_RESTORE();
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return (const void *) (cache_page | (phys_offs & (SPI_FLASH_MMU_PAGE_SIZE-1)));
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}
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}
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DPORT_INTERRUPT_RESTORE();
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return NULL;
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}
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static bool IRAM_ATTR is_page_mapped_in_cache(uint32_t phys_page)
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{
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int start[2], end[2];
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/* SPI_FLASH_MMAP_DATA */
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start[0] = 0;
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end[0] = 64;
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/* SPI_FLASH_MMAP_INST */
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start[1] = PRO_IRAM0_FIRST_USABLE_PAGE;
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end[1] = 256;
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DPORT_INTERRUPT_DISABLE();
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for (int j = 0; j < 2; j++) {
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for (int i = start[j]; i < end[j]; i++) {
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if (DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]) == phys_page) {
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DPORT_INTERRUPT_RESTORE();
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return true;
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}
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}
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}
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DPORT_INTERRUPT_RESTORE();
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return false;
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}
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/* Validates if given flash address has corresponding cache mapping, if yes, flushes cache memories */
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IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
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{
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/* align start_addr & length to full MMU pages */
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uint32_t page_start_addr = start_addr & ~(SPI_FLASH_MMU_PAGE_SIZE-1);
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length += (start_addr - page_start_addr);
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length = (length + SPI_FLASH_MMU_PAGE_SIZE - 1) & ~(SPI_FLASH_MMU_PAGE_SIZE-1);
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for (uint32_t addr = page_start_addr; addr < page_start_addr + length; addr += SPI_FLASH_MMU_PAGE_SIZE) {
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uint32_t page = addr / SPI_FLASH_MMU_PAGE_SIZE;
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if (page >= 256) {
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return false; /* invalid address */
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}
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if (is_page_mapped_in_cache(page)) {
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#if CONFIG_SPIRAM_SUPPORT
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esp_spiram_writeback_cache();
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#endif
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Cache_Flush(0);
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#ifndef CONFIG_FREERTOS_UNICORE
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Cache_Flush(1);
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#endif
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return true;
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|
}
|
|
}
|
|
return false;
|
|
}
|