91e62f4e37
timer group interrupt enable is controled by level_int_ena instead of int_ena Closes https://github.com/espressif/esp-idf/issues/5103
331 lines
9.1 KiB
C
331 lines
9.1 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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// The HAL layer for Timer Group.
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// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "hal/timer_ll.h"
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#include "hal/timer_types.h"
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#include "soc/timer_group_caps.h"
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/**
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* Context that should be maintained by both the driver and the HAL
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*/
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typedef struct {
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timg_dev_t *dev;
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timer_idx_t idx;
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} timer_hal_context_t;
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/**
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* @brief Init the timer hal. This function should be called first before other hal layer function is called
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*
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* @param hal Context of the HAL layer
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* @param group_num The timer group number
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* @param timer_num The timer number
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*
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* @return None
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*/
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void timer_hal_init(timer_hal_context_t *hal, timer_group_t group_num, timer_idx_t timer_num);
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/**
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* @brief Get interrupt status register address and corresponding control bits mask
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*
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* @param hal Context of the HAL layer
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* @param status_reg[out] interrupt status register address
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* @param mask_bit[out] control bits mask
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*/
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void timer_hal_get_status_reg_mask_bit(timer_hal_context_t *hal, uint32_t *status_reg, uint32_t *mask_bit);
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/**
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* @brief Set timer clock prescale value
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*
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* @param hal Context of the HAL layer
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* @param divider Prescale value
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*
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* @return None
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*/
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#define timer_hal_set_divider(hal, divider) timer_ll_set_divider((hal)->dev, (hal)->idx, divider)
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/**
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* @brief Get timer clock prescale value
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*
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* @param hal Context of the HAL layer
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* @param divider Pointer to accept the prescale value
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*
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* @return None
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*/
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#define timer_hal_get_divider(hal, divider) timer_ll_get_divider((hal)->dev, (hal)->idx, divider)
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/**
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* @brief Load counter value into time-base counter
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*
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* @param hal Context of the HAL layer
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* @param load_val Counter value
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*
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* @return None
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*/
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#define timer_hal_set_counter_value(hal, load_val) timer_ll_set_counter_value((hal)->dev, (hal)->idx, load_val)
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/**
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* @brief Get counter value from time-base counter
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*
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* @param hal Context of the HAL layer
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* @param timer_val Pointer to accept the counter value
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*
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* @return None
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*/
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#define timer_hal_get_counter_value(hal, timer_val) timer_ll_get_counter_value((hal)->dev, (hal)->idx, timer_val)
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/**
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* @brief Set counter mode, include increment mode and decrement mode.
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*
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* @param hal Context of the HAL layer
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* @param increase_en True to increment mode, fasle to decrement mode
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*
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* @return None
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*/
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#define timer_hal_set_counter_increase(hal, increase_en) timer_ll_set_counter_increase((hal)->dev, (hal)->idx, increase_en)
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/**
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* @brief Get counter mode, include increment mode and decrement mode.
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*
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* @param hal Context of the HAL layer
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* @param counter_dir Pointer to accept the counter mode
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*
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* @return
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* - true Increment mode
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* - false Decrement mode
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*/
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#define timer_hal_get_counter_increase(hal) timer_ll_get_counter_increase((hal)->dev, (hal)->idx)
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/**
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* @brief Set counter status, enable or disable counter.
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*
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* @param hal Context of the HAL layer
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* @param counter_en True to enable counter, false to disable counter
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*
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* @return None
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*/
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#define timer_hal_set_counter_enable(hal, counter_en) timer_ll_set_counter_enable((hal)->dev, (hal)->idx, counter_en)
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/**
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* @brief Get counter status.
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*
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* @param hal Context of the HAL layer
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*
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* @return
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* - true Enable counter
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* - false Disable conuter
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*/
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#define timer_hal_get_counter_enable(hal) timer_ll_get_counter_enable((hal)->dev, (hal)->idx)
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/**
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* @brief Set auto reload mode.
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*
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* @param hal Context of the HAL layer
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* @param auto_reload_en True to enable auto reload mode, flase to disable auto reload mode
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*
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* @return None
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*/
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#define timer_hal_set_auto_reload(hal, auto_reload_en) timer_ll_set_auto_reload((hal)->dev, (hal)->idx, auto_reload_en)
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/**
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* @brief Get auto reload mode.
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*
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* @param hal Context of the HAL layer
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*
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* @return
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* - true Enable auto reload mode
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* - false Disable auto reload mode
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*/
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#define timer_hal_get_auto_reload(hal) timer_ll_get_auto_reload((hal)->dev, (hal)->idx)
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/**
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* @brief Set the counter value to trigger the alarm.
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*
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* @param hal Context of the HAL layer
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* @param alarm_value Counter value to trigger the alarm
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*
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* @return None
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*/
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#define timer_hal_set_alarm_value(hal, alarm_value) timer_ll_set_alarm_value((hal)->dev, (hal)->idx, alarm_value)
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/**
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* @brief Get the counter value to trigger the alarm.
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*
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* @param hal Context of the HAL layer
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* @param alarm_value Pointer to accept the counter value to trigger the alarm
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*
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* @return None
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*/
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#define timer_hal_get_alarm_value(hal, alarm_value) timer_ll_get_alarm_value((hal)->dev, (hal)->idx, alarm_value)
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/**
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* @brief Set the alarm status, enable or disable the alarm.
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*
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* @param hal Context of the HAL layer
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* @param alarm_en True to enable alarm, false to disable alarm
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*
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* @return None
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*/
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#define timer_hal_set_alarm_enable(hal, alarm_en) timer_ll_set_alarm_enable((hal)->dev, (hal)->idx, alarm_en)
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/**
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* @brief Get the alarm status.
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*
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* @param hal Context of the HAL layer
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*
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* @return
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* - true Enable alarm
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* - false Disable alarm
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*/
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#define timer_hal_get_alarm_enable(hal) timer_ll_get_alarm_enable((hal)->dev, (hal)->idx)
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/**
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* @brief Set the level interrupt status, enable or disable the level interrupt.
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*
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* @param hal Context of the HAL layer
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* @param level_int_en True to enable level interrupt, false to disable level interrupt
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*
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* @return None
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*/
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#define timer_hal_set_level_int_enable(hal, level_int_en) timer_ll_set_level_int_enable((hal)->dev, (hal)->idx, level_int_en)
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/**
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* @brief Get the level interrupt status.
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*
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* @param hal Context of the HAL layer
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*
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* @return
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* - true Enable level interrupt
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* - false Disable level interrupt
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*/
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#define timer_hal_get_level_int_enable(hal) timer_ll_get_level_int_enable((hal)->dev, (hal)->idx)
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/**
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* @brief Set the edge interrupt status, enable or disable the edge interrupt.
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*
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* @param hal Context of the HAL layer
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* @param edge_int_en True to enable edge interrupt, false to disable edge interrupt
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*
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* @return None
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*/
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#define timer_hal_set_edge_int_enable(hal, edge_int_en) timer_ll_set_edge_int_enable((hal)->dev, (hal)->idx, edge_int_en)
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/**
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* @brief Get the edge interrupt status.
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*
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* @param hal Context of the HAL layer
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*
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* @return
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* - true Enable edge interrupt
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* - false Disable edge interrupt
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*/
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#define timer_hal_get_edge_int_enable(hal) timer_ll_get_edge_int_enable((hal)->dev, (hal)->idx)
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/**
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* @brief Enable timer interrupt.
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*
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* @param hal Context of the HAL layer
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*
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* @return None
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*/
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#define timer_hal_intr_enable(hal) timer_ll_intr_enable((hal)->dev, (hal)->idx)
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/**
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* @brief Disable timer interrupt.
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*
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* @param hal Context of the HAL layer
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*
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* @return None
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*/
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#define timer_hal_intr_disable(hal) timer_ll_intr_disable((hal)->dev, (hal)->idx)
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/**
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* @brief Clear interrupt status.
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*
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* @param hal Context of the HAL layer
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*
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* @return None
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*/
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#define timer_hal_clear_intr_status(hal) timer_ll_clear_intr_status((hal)->dev, (hal)->idx)
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/**
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* @brief Get interrupt status.
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*
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* @param hal Context of the HAL layer
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* @param intr_status Interrupt status
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*
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* @return None
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*/
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#define timer_hal_get_intr_status(hal, intr_status) timer_ll_get_intr_status((hal)->dev, intr_status)
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/**
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* @brief Get interrupt raw status.
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*
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* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
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* @param intr_raw_status Interrupt raw status
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*
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* @return None
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*/
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#define timer_hal_get_intr_raw_status(group_num, intr_raw_status) timer_ll_get_intr_raw_status(group_num, intr_raw_status)
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/**
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* @brief Get interrupt status register address.
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*
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* @param hal Context of the HAL layer
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*
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* @return Interrupt status register address
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*/
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#define timer_hal_get_intr_status_reg(hal) timer_ll_get_intr_status_reg((hal)->dev)
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#ifdef SOC_TIMER_GROUP_SUPPORT_XTAL
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/**
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* @brief Set clock source.
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*
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* @param hal Context of the HAL layer
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* @param use_xtal_en True to use XTAL clock, flase to use APB clock
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*
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* @return None
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*/
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#define timer_hal_set_use_xtal(hal, use_xtal_en) timer_ll_set_use_xtal((hal)->dev, (hal)->idx, use_xtal_en)
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/**
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* @brief Get clock source.
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*
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* @param hal Context of the HAL layer
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*
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* @return
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* - true Use XTAL clock
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* - false Use APB clock
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*/
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#define timer_hal_get_use_xtal(hal) timer_ll_get_use_xtal((hal)->dev, (hal)->idx)
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#endif
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#ifdef __cplusplus
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}
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#endif
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