154 lines
6.2 KiB
C
154 lines
6.2 KiB
C
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <esp_types.h>
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#include "esp_flash_err.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Definition of a common transaction. Also holds the return value. */
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typedef struct {
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uint8_t command; ///< Command to send, always 8bits
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uint8_t mosi_len; ///< Output data length, in bytes
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uint8_t miso_len; ///< Input data length, in bytes
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uint8_t address_bitlen; ///< Length of address in bits, set to 0 if command does not need an address
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uint32_t address; ///< Address to perform operation on
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const uint8_t *mosi_data; ///< Output data to salve
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uint8_t *miso_data; ///< [out] Input data from slave, little endian
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} spi_flash_trans_t;
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/**
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* @brief SPI flash clock speed values, always refer to them by the enum rather
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* than the actual value (more speed may be appended into the list).
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*
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* A strategy to select the maximum allowed speed is to enumerate from the
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* ``ESP_FLSH_SPEED_MAX-1`` or highest frequency supported by your flash, and
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* decrease the speed until the probing success.
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*/
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typedef enum {
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ESP_FLASH_5MHZ = 0, ///< The flash runs under 5MHz
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ESP_FLASH_10MHZ, ///< The flash runs under 10MHz
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ESP_FLASH_20MHZ, ///< The flash runs under 20MHz
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ESP_FLASH_26MHZ, ///< The flash runs under 26MHz
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ESP_FLASH_40MHZ, ///< The flash runs under 40MHz
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ESP_FLASH_80MHZ, ///< The flash runs under 80MHz
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ESP_FLASH_SPEED_MAX, ///< The maximum frequency supported by the host is ``ESP_FLASH_SPEED_MAX-1``.
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} esp_flash_speed_t;
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///Lowest speed supported by the driver, currently 5 MHz
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#define ESP_FLASH_SPEED_MIN ESP_FLASH_5MHZ
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/** @brief Mode used for reading from SPI flash */
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typedef enum {
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SPI_FLASH_SLOWRD = 0, ///< Data read using single I/O, some limits on speed
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SPI_FLASH_FASTRD, ///< Data read using single I/O, no limit on speed
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SPI_FLASH_DOUT, ///< Data read using dual I/O
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SPI_FLASH_DIO, ///< Both address & data transferred using dual I/O
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SPI_FLASH_QOUT, ///< Data read using quad I/O
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SPI_FLASH_QIO, ///< Both address & data transferred using quad I/O
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SPI_FLASH_READ_MODE_MAX, ///< The fastest io mode supported by the host is ``ESP_FLASH_READ_MODE_MAX-1``.
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} esp_flash_io_mode_t;
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///Slowest io mode supported by ESP32, currently SlowRd
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#define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD
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struct spi_flash_host_driver_t;
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typedef struct spi_flash_host_driver_t spi_flash_host_driver_t;
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/** Host driver configuration and context structure. */
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struct spi_flash_host_driver_t {
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/**
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* Configuration and static data used by the specific host driver. The type
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* is determined by the host driver.
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*/
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void *driver_data;
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/**
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* Configure the device-related register before transactions. This saves
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* some time to re-configure those registers when we send continuously
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*/
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esp_err_t (*dev_config)(spi_flash_host_driver_t *driver);
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/**
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* Send an user-defined spi transaction to the device.
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*/
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esp_err_t (*common_command)(spi_flash_host_driver_t *driver, spi_flash_trans_t *t);
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/**
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* Read flash ID.
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*/
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esp_err_t (*read_id)(spi_flash_host_driver_t *driver, uint32_t *id);
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/**
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* Erase whole flash chip.
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*/
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void (*erase_chip)(spi_flash_host_driver_t *driver);
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/**
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* Erase a specific sector by its start address.
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*/
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void (*erase_sector)(spi_flash_host_driver_t *driver, uint32_t start_address);
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/**
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* Erase a specific block by its start address.
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*/
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void (*erase_block)(spi_flash_host_driver_t *driver, uint32_t start_address);
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/**
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* Read the status of the flash chip.
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*/
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esp_err_t (*read_status)(spi_flash_host_driver_t *driver, uint8_t *out_sr);
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/**
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* Disable write protection.
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*/
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esp_err_t (*set_write_protect)(spi_flash_host_driver_t *driver, bool wp);
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/**
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* Program a page of the flash. Check ``max_write_bytes`` for the maximum allowed writing length.
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*/
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void (*program_page)(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
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/** Check whether need to allocate new buffer to write */
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bool (*supports_direct_write)(spi_flash_host_driver_t *driver, const void *p);
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/** Check whether need to allocate new buffer to read */
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bool (*supports_direct_read)(spi_flash_host_driver_t *driver, const void *p);
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/** maximum length of program_page */
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int max_write_bytes;
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/**
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* Read data from the flash. Check ``max_read_bytes`` for the maximum allowed reading length.
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*/
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esp_err_t (*read)(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
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/** maximum length of read */
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int max_read_bytes;
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/**
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* Check whether the host is idle to perform new operations.
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*/
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bool (*host_idle)(spi_flash_host_driver_t *driver);
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/**
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* Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode.
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*/
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esp_err_t (*configure_host_io_mode)(spi_flash_host_driver_t *driver, uint32_t command,
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uint32_t addr_bitlen, int dummy_bitlen_base,
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esp_flash_io_mode_t io_mode);
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/**
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* Internal use, poll the HW until the last operation is done.
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*/
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void (*poll_cmd_done)(spi_flash_host_driver_t *driver);
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/**
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* For some host (SPI1), they are shared with a cache. When the data is
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* modified, the cache needs to be flushed. Left NULL if not supported.
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*/
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esp_err_t (*flush_cache)(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size);
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};
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#ifdef __cplusplus
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}
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#endif
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