219 lines
8 KiB
C
219 lines
8 KiB
C
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*******************************************************************************
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* NOTICE
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* The HAL is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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// The HAL layer for SPI Flash (common part)
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#pragma once
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#include "hal/spi_flash_ll.h"
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#include "hal/spi_types.h"
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#include "hal/spi_flash_types.h"
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#include "soc/soc_memory_layout.h"
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/* Hardware host-specific constants */
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#define SPI_FLASH_HAL_MAX_WRITE_BYTES 64
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#define SPI_FLASH_HAL_MAX_READ_BYTES 64
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/**
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* Generic driver context structure for all chips using the SPI peripheral.
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* Include this into the HEAD of the driver data for other driver
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* implementations that also use the SPI peripheral.
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*/
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typedef struct {
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spi_dev_t *spi; ///< Pointer to SPI peripheral registers (SP1, SPI2 or SPI3). Set before initialisation.
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int cs_num; ///< Which cs pin is used, 0-2.
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int extra_dummy;
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spi_flash_ll_clock_reg_t clock_conf;
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} spi_flash_memspi_data_t;
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/// Configuration structure for the SPI driver.
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typedef struct {
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spi_host_device_t host_id; ///< SPI peripheral ID.
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int cs_num; ///< Which cs pin is used, 0-2.
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bool iomux; ///< Whether the IOMUX is used, used for timing compensation.
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int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation.
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esp_flash_speed_t speed;///< SPI flash clock speed to work at.
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} spi_flash_memspi_config_t;
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/**
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* Configure SPI flash hal settings.
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*
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* @param data Buffer to hold configured data, the buffer should be in DRAM to be available when cache disabled
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* @param cfg Configurations to set
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*
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* @return
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* - ESP_OK: success
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* - ESP_ERR_INVALID_ARG: the data buffer is not in the DRAM.
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*/
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esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_memspi_config_t *cfg);
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/**
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* Configure the device-related register before transactions.
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*
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* @param driver The driver context.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver);
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/**
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* Send an user-defined spi transaction to the device.
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*
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* @note This is usually used when the memspi interface doesn't support some
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* particular commands. Since this function supports timing compensation, it is
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* also used to receive some data when the frequency is high.
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*
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* @param driver The driver context.
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* @param trans The transaction to send, also holds the received data.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *driver, spi_flash_trans_t *trans);
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/**
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* Erase whole flash chip by using the erase chip (C7h) command.
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*
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* @param driver The driver context.
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*/
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void spi_flash_hal_erase_chip(spi_flash_host_driver_t *driver);
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/**
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* Erase a specific sector by its start address through the sector erase (20h)
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* command.
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*
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* @param driver The driver context.
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* @param start_address Start address of the sector to erase.
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*/
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void spi_flash_hal_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address);
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/**
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* Erase a specific 64KB block by its start address through the 64KB block
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* erase (D8h) command.
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*
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* @param driver The driver context.
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* @param start_address Start address of the block to erase.
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*/
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void spi_flash_hal_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address);
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/**
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* Program a page of the flash using the page program (02h) command.
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*
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* @param driver The driver context.
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* @param address Address of the page to program
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* @param buffer Data to program
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* @param length Size of the buffer in bytes, no larger than ``SPI_FLASH_HAL_MAX_WRITE_BYTES`` (64) bytes.
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*/
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void spi_flash_hal_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length);
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/**
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* Read from the flash. Call ``spi_flash_hal_configure_host_read_mode`` to
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* configure the read command before calling this function.
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*
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* @param driver The driver context.
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* @param buffer Buffer to store the read data
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* @param address Address to read
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* @param length Length to read, no larger than ``SPI_FLASH_HAL_MAX_READ_BYTES`` (64) bytes.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len);
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/**
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* @brief Send the write enable (06h) or write disable (04h) command to the flash chip.
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*
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* @param driver The driver context.
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* @param wp true to enable the write protection, otherwise false.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, bool wp);
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/**
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* Check whether the SPI host is idle and can perform other operations.
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*
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* @param driver The driver context.
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*
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* @return ture if idle, otherwise false.
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*/
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bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver);
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/**
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* @brief Configure the SPI host hardware registers for the specified io mode.
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*
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* Note that calling this configures SPI host registers, so if running any
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* other commands as part of set_io_mode() then these must be run before
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* calling this function.
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*
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* The command value, address length and dummy cycles are configured according
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* to the format of read commands:
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*
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* - command: 8 bits, value set.
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* - address: 24 bits
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* - dummy: cycles to compensate the input delay
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* - out & in data: 0 bits.
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*
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* The following commands still need to:
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*
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* - Read data: set address value and data (length and contents), no need
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* to touch command and dummy phases.
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* - Common read: set command value, address value (or length to 0 if not used)
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* - Common write: set command value, address value (or length to 0 if not
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* used), disable dummy phase, and set output data.
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*
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* @param driver The driver context
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* @param io_mode The HW read mode to use
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* @param addr_bitlen Length of the address phase, in bits
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* @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing.
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* @param command Actual reading command to send to flash chip on the bus.
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*
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* @return always return ESP_OK.
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*/
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esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_driver_t *driver, uint32_t command, uint32_t addr_bitlen,
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int dummy_cyclelen_base, esp_flash_io_mode_t io_mode);
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/**
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* Poll until the last operation is done.
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*
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* @param driver The driver context.
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*/
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void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *driver);
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/**
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* Check whether the given buffer can be used as the write buffer directly. If 'chip' is connected to the main SPI bus, we can only write directly from
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* regions that are accessible ith cache disabled. *
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*
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* @param driver The driver context
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* @param p The buffer holding data to send.
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*
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* @return True if the buffer can be used to send data, otherwise false.
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*/
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bool spi_flash_hal_supports_direct_write(spi_flash_host_driver_t *driver, const void *p);
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/**
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* Check whether the given buffer can be used as the read buffer directly. If 'chip' is connected to the main SPI bus, we can only read directly from
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* regions that are accessible ith cache disabled. *
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*
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* @param driver The driver context
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* @param p The buffer to hold the received data.
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*
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* @return True if the buffer can be used to receive data, otherwise false.
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*/
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bool spi_flash_hal_supports_direct_read(spi_flash_host_driver_t *driver, const void *p);
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