341 lines
16 KiB
C
341 lines
16 KiB
C
#pragma once
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#include "soc/adc_caps.h"
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#include "sdkconfig.h"
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#include <stdbool.h>
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/**
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* @brief ADC units selected handle.
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*
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* @note For ADC digital controller(DMA mode), ESP32 don't support `ADC_UNIT_2`, `ADC_UNIT_BOTH`, `ADC_UNIT_ALTER`.
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*/
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typedef enum {
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ADC_UNIT_1 = 1, /*!< SAR ADC 1. */
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ADC_UNIT_2 = 2, /*!< SAR ADC 2. */
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ADC_UNIT_BOTH = 3, /*!< SAR ADC 1 and 2. */
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ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode. */
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ADC_UNIT_MAX,
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} adc_unit_t;
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/**
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* @brief ADC channels handle. See ``adc1_channel_t``, ``adc2_channel_t``.
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*
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* @note For ESP32 ADC1, don't support `ADC_CHANNEL_8`, `ADC_CHANNEL_9`. See ``adc1_channel_t``.
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*/
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typedef enum {
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ADC_CHANNEL_0 = 0, /*!< ADC channel */
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ADC_CHANNEL_1, /*!< ADC channel */
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ADC_CHANNEL_2, /*!< ADC channel */
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ADC_CHANNEL_3, /*!< ADC channel */
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ADC_CHANNEL_4, /*!< ADC channel */
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ADC_CHANNEL_5, /*!< ADC channel */
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ADC_CHANNEL_6, /*!< ADC channel */
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ADC_CHANNEL_7, /*!< ADC channel */
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ADC_CHANNEL_8, /*!< ADC channel */
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ADC_CHANNEL_9, /*!< ADC channel */
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ADC_CHANNEL_MAX,
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} adc_channel_t;
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/**
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* @brief ADC attenuation parameter. Different parameters determine the range of the ADC. See ``adc1_config_channel_atten``.
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*/
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typedef enum {
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ADC_ATTEN_DB_0 = 0, /*!<The input voltage of ADC will be reduced to about 1/1 */
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ADC_ATTEN_DB_2_5 = 1, /*!<The input voltage of ADC will be reduced to about 1/1.34 */
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ADC_ATTEN_DB_6 = 2, /*!<The input voltage of ADC will be reduced to about 1/2 */
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ADC_ATTEN_DB_11 = 3, /*!<The input voltage of ADC will be reduced to about 1/3.6*/
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ADC_ATTEN_MAX,
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} adc_atten_t;
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/**
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* @brief ESP32 ADC DMA source selection.
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*
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* @note It's be deprecated in ESP32S2. Beacause ESP32S2 don't use I2S DMA.
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*/
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typedef enum {
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ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal */
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ADC_I2S_DATA_SRC_ADC = 1, /*!< I2S data from ADC */
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ADC_I2S_DATA_SRC_MAX,
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} adc_i2s_source_t;
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/**
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* @brief ADC resolution setting option.
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*
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* @note For ESP32S2. Only support 13 bit resolution.
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* For ESP32. Don't support 13 bit resolution.
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*/
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typedef enum {
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ADC_WIDTH_BIT_9 = 0, /*!< ADC capture width is 9Bit. Only ESP32 is supported. */
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ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. Only ESP32 is supported. */
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ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. Only ESP32 is supported. */
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ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. Only ESP32 is supported. */
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. Only ESP32S2 is supported. */
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#endif
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ADC_WIDTH_MAX,
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} adc_bits_width_t;
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/**
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* @brief ADC digital controller (DMA mode) output data format option.
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*/
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typedef enum {
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ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
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Note: In single convert mode. */
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ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
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Note: In multi or alter convert mode. */
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ADC_DIGI_FORMAT_MAX,
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} adc_digi_output_format_t;
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/**
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* @brief ADC digital controller (DMA mode) output data format.
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* Used to analyze the acquired ADC (DMA) data.
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*
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* @note ESP32S2:
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* Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
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*/
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typedef struct {
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union {
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struct {
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uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
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uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
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struct {
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uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
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uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
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} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
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uint16_t val;
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};
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} adc_digi_output_data_t;
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief ADC digital controller (DMA mode) clock system setting.
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* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
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*/
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typedef struct {
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bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
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uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
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Note: When a higher frequency clock is used (the division factor is less than 9),
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the ADC reading value will be slightly offset. */
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uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
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uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
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} adc_digi_clk_t;
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/**
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* @brief ADC arbiter work mode option.
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*
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* @note ESP32S2: Only ADC2 support arbiter.
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*/
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typedef enum {
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ADC_ARB_MODE_SHIELD,/*!<Force shield arbiter, Select the highest priority controller to work. */
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ADC_ARB_MODE_FIX, /*!<Fixed priority switch controller mode. */
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ADC_ARB_MODE_LOOP, /*!<Loop priority switch controller mode. Each controller has the same priority,
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and the arbiter will switch to the next controller after the measurement is completed. */
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} adc_arbiter_mode_t;
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/**
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* @brief ADC arbiter work mode and priority setting.
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*
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* @note ESP32S2: Only ADC2 support arbiter.
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*/
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typedef struct {
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adc_arbiter_mode_t mode; /*!<Refer to ``adc_arbiter_mode_t``. Note: only support ADC2. */
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uint8_t rtc_pri; /*!<RTC controller priority. Range: 0 ~ 2. */
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uint8_t dig_pri; /*!<Digital controller priority. Range: 0 ~ 2. */
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uint8_t pwdet_pri; /*!<Wi-Fi controller priority. Range: 0 ~ 2. */
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} adc_arbiter_t;
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/**
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* @brief ADC arbiter default configuration.
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*
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* @note ESP32S2: Only ADC2 support arbiter.
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*/
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#define ADC_ARBITER_CONFIG_DEFAULT() { \
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.mode = ADC_ARB_MODE_FIX, \
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.rtc_pri = 1, \
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.dig_pri = 0, \
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.pwdet_pri = 2, \
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}
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/**
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* @brief ADC digital controller (DMA mode) work mode.
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*
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* @note The conversion mode affects the sampling frequency:
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* SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
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* SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
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* BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
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* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
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*/
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typedef enum {
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ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1. */
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ADC_CONV_SINGLE_UNIT_2 = 2, /*!< SAR ADC 2. */
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ADC_CONV_BOTH_UNIT = 3, /*!< SAR ADC 1 and 2. */
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ADC_CONV_ALTER_UNIT = 7, /*!< SAR ADC 1 and 2 alternative mode. */
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ADC_CONV_UNIT_MAX,
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} adc_digi_convert_mode_t;
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/**
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* @brief ADC digital controller (DMA mode) conversion rules setting.
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*/
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typedef struct {
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union {
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struct {
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uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration.
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0: input voltage * 1;
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1: input voltage * 1/1.34;
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2: input voltage * 1/2;
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3: input voltage * 1/3.6. */
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uint8_t reserved: 2; /*!< reserved0 */
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uint8_t channel: 4; /*!< ADC channel index. */
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};
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uint8_t val; /*!< Raw entry value */
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};
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} adc_digi_pattern_table_t;
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/**
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* @brief ADC digital controller (DMA mode) interrupt type options.
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*/
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typedef enum {
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ADC_DIGI_INTR_MASK_MONITOR = 0x1,
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ADC_DIGI_INTR_MASK_MEAS_DONE = 0x2,
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ADC_DIGI_INTR_MASK_ALL = 0x3,
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} adc_digi_intr_t;
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/**
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* @brief ADC digital controller (DMA mode) configuration parameters.
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*
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* Example setting: Use ADC1 channel0 to measure voltage, the sampling rate is required to be 1KHz:
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* +---------------------+--------+--------+--------+
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* | sample rate | 1KHz | 1KHz | 1KHz |
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* +---------------------+--------+--------+--------+
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* | conv_mode | single | both | alter |
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* | adc1_pattern_len | 1 | 1 | 1 |
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* | dig_clk.use_apll | 0 | 0 | 0 |
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* | dig_clk.div_num | 99 | 99 | 99 |
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* | dig_clk.div_b | 0 | 0 | 0 |
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* | dig_clk.div_a | 0 | 0 | 0 |
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* | interval | 400 | 400 | 200 |
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* +---------------------+--------+--------+--------+
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* | `trigger_meas_freq` | 1KHz | 1KHz | 2KHz |
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* +---------------------+--------+--------+--------+
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*
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* Explain the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA output:
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* +---------------------+--------+--------+--------+
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* | conv_mode | single | both | alter |
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* +---------------------+--------+--------+--------+
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* | trigger meas times | 1 | 1 | 1 |
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* +---------------------+--------+--------+--------+
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* | conv_limit_num | +1 | +1 | +1 |
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* | dma_eof_num | +1 | +2 | +1 |
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* | dma output (byte) | +2 | +4 | +2 |
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* +---------------------+--------+--------+--------+
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*/
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typedef struct {
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bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times.
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If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */
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uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */
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uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting).
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The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
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resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
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pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
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uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */
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adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
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adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to ``adc1_pattern`` */
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adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */
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adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */
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uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement.
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The unit is the divided clock. Range: 40 ~ 4095.
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Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
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Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */
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adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t`` */
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uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller.
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If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA.
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Note: The converted data in the DMA in link buffer will be multiple of two bytes. */
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} adc_digi_config_t;
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/**
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* @brief ADC digital controller (DMA mode) filter index options.
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*
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* @note For ESP32S2, The filter object of the ADC is fixed.
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*/
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typedef enum {
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ADC_DIGI_FILTER_IDX0 = 0, /*!<The filter index 0.
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For ESP32S2, It can only be used to filter all enabled channels of ADC1 unit at the same time. */
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ADC_DIGI_FILTER_IDX1, /*!<The filter index 1.
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For ESP32S2, It can only be used to filter all enabled channels of ADC2 unit at the same time. */
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ADC_DIGI_FILTER_IDX_MAX
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} adc_digi_filter_idx_t;
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/**
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* @brief ADC digital controller (DMA mode) filter type options.
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* Expression: filter_data = (k-1)/k * last_data + new_data / k.
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*/
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typedef enum {
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ADC_DIGI_FILTER_IIR_2 = 0, /*!<The filter mode is first-order IIR filter. The coefficient is 2. */
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ADC_DIGI_FILTER_IIR_4, /*!<The filter mode is first-order IIR filter. The coefficient is 4. */
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ADC_DIGI_FILTER_IIR_8, /*!<The filter mode is first-order IIR filter. The coefficient is 8. */
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ADC_DIGI_FILTER_IIR_16, /*!<The filter mode is first-order IIR filter. The coefficient is 16. */
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ADC_DIGI_FILTER_IIR_64, /*!<The filter mode is first-order IIR filter. The coefficient is 64. */
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ADC_DIGI_FILTER_IIR_MAX
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} adc_digi_filter_mode_t;
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/**
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* @brief ADC digital controller (DMA mode) filter configuration.
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*
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* @note For ESP32S2, The filter object of the ADC is fixed.
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* @note For ESP32S2, The filter object is always all enabled channels.
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*/
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typedef struct {
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adc_unit_t adc_unit; /*!<Set adc unit number for filter.
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For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time. */
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adc_channel_t channel; /*!<Set adc channel number for filter.
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For ESP32S2, it's always `ADC_CHANNEL_MAX` */
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adc_digi_filter_mode_t mode;/*!<Set adc filter mode for filter. See ``adc_digi_filter_mode_t``. */
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} adc_digi_filter_t;
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/**
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* @brief ADC digital controller (DMA mode) monitor index options.
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*
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* @note For ESP32S2, The monitor object of the ADC is fixed.
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*/
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typedef enum {
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ADC_DIGI_MONITOR_IDX0 = 0, /*!<The monitor index 0.
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For ESP32S2, It can only be used to monitor all enabled channels of ADC1 unit at the same time. */
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ADC_DIGI_MONITOR_IDX1, /*!<The monitor index 1.
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For ESP32S2, It can only be used to monitor all enabled channels of ADC2 unit at the same time. */
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ADC_DIGI_MONITOR_IDX_MAX
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} adc_digi_monitor_idx_t;
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/**
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* @brief Set monitor mode of adc digital controller.
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* MONITOR_HIGH:If ADC_OUT > threshold, Generates monitor interrupt.
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* MONITOR_LOW: If ADC_OUT < threshold, Generates monitor interrupt.
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*/
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typedef enum {
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ADC_DIGI_MONITOR_HIGH = 0, /*!<If ADC_OUT > threshold, Generates monitor interrupt. */
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ADC_DIGI_MONITOR_LOW, /*!<If ADC_OUT < threshold, Generates monitor interrupt. */
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ADC_DIGI_MONITOR_MAX
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} adc_digi_monitor_mode_t;
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/**
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* @brief ADC digital controller (DMA mode) monitor configuration.
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*
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* @note For ESP32S2, The monitor object of the ADC is fixed.
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* @note For ESP32S2, The monitor object is always all enabled channels.
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*/
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typedef struct {
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adc_unit_t adc_unit; /*!<Set adc unit number for monitor.
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For ESP32S2, monitor IDX0/IDX1 can only be used to monitor all enabled channels of ADC1/ADC2 unit at the same time. */
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adc_channel_t channel; /*!<Set adc channel number for monitor.
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For ESP32S2, it's always `ADC_CHANNEL_MAX` */
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adc_digi_monitor_mode_t mode; /*!<Set adc monitor mode. See ``adc_digi_monitor_mode_t``. */
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uint32_t threshold; /*!<Set monitor threshold of adc digital controller. */
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} adc_digi_monitor_t;
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#endif // CONFIG_IDF_TARGET_ESP32S2
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