2b7681ec4f
There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
102 lines
3.8 KiB
C
102 lines
3.8 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "hal/spi_flash_hal.h"
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/** Default configuration for the memspi (high speed version) */
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#define ESP_FLASH_DEFAULT_HOST_DRIVER() (spi_flash_host_driver_t) { \
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.dev_config = spi_flash_hal_device_config, \
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.common_command = spi_flash_hal_common_command, \
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.read_id = memspi_host_read_id_hs, \
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.erase_chip = spi_flash_hal_erase_chip, \
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.erase_sector = spi_flash_hal_erase_sector, \
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.erase_block = spi_flash_hal_erase_block, \
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.read_status = memspi_host_read_status_hs, \
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.set_write_protect = spi_flash_hal_set_write_protect, \
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.supports_direct_write = spi_flash_hal_supports_direct_write, \
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.supports_direct_read = spi_flash_hal_supports_direct_read, \
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.program_page = spi_flash_hal_program_page, \
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.max_write_bytes = SPI_FLASH_HAL_MAX_WRITE_BYTES, \
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.read = spi_flash_hal_read, \
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.max_read_bytes = SPI_FLASH_HAL_MAX_READ_BYTES, \
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.host_idle = spi_flash_hal_host_idle, \
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.configure_host_io_mode = spi_flash_hal_configure_host_io_mode, \
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.poll_cmd_done = spi_flash_hal_poll_cmd_done, \
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.flush_cache = memspi_host_flush_cache, \
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}
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/// configuration for the memspi host
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typedef spi_flash_memspi_config_t memspi_host_config_t;
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/// context for the memspi host
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typedef spi_flash_memspi_data_t memspi_host_data_t;
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/**
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* Initialize the memory SPI host.
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*
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* @param host Pointer to the host structure.
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* @param data Pointer to allocated space to hold the context of host driver.
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* @param cfg Pointer to configuration structure
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*
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* @return always return ESP_OK
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*/
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esp_err_t memspi_host_init_pointers(spi_flash_host_driver_t *host, memspi_host_data_t *data, const memspi_host_config_t *cfg);
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/*******************************************************************************
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* NOTICE
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* Rest part of this file are part of the HAL layer
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* The HAL is not public api, don't use in application code.
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* See readme.md in soc/include/hal/readme.md
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******************************************************************************/
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/**
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* @brief Read the Status Register read from RDSR (05h).
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*
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* High speed implementation of RDID through memspi interface relying on the
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* ``common_command``.
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*
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* @param driver The driver context.
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* @param id Output of the read ID from the slave.
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*
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* @return
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* - ESP_OK: if success
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* - ESP_ERR_FLASH_NO_RESPONSE: if no response from chip
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* - or other cases from ``spi_hal_common_command``
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*/
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esp_err_t memspi_host_read_id_hs(spi_flash_host_driver_t *driver, uint32_t *id);
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/**
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* High speed implementation of RDSR through memspi interface relying on the
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* ``common_command``.
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*
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* @param driver The driver context.
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* @param id Output of the read ID from the slave.
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*
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* @return
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* - ESP_OK: if success
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* - or other cases from ``spi_hal_common_command``
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*/
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esp_err_t memspi_host_read_status_hs(spi_flash_host_driver_t *driver, uint8_t *out_sr);
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/**
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* Flush the cache (if needed) after the contents are modified.
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*
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* @param driver The driver context.
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* @param addr Start address of the modified region
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* @param size Size of the region modified.
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*
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* @return always ESP_OK.
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*/
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esp_err_t memspi_host_flush_cache(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size);
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