144 lines
4.1 KiB
C
144 lines
4.1 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include <string.h>
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#include "rom/ets_sys.h"
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#include "rom/gpio.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/gpio_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/emac_reg_v2.h"
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#include "soc/emac_ex_reg.h"
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#include "esp_log.h"
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#include "driver/gpio.h"
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#include "sdkconfig.h"
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#include "emac_common.h"
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static const char *TAG = "emac";
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void emac_enable_flowctrl(void)
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{
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REG_SET_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_TRANSMIT_FLOW_CONTROL_ENABLE);
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REG_SET_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_RECEIVE_FLOW_CONTROL_ENABLE);
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REG_CLR_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_DISABLE_ZERO_QUANTA_PAUSE);
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REG_SET_FIELD(EMAC_GMACFLOWCONTROL_REG, EMAC_PAUSE_TIME, 0x1648);
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REG_SET_FIELD(EMAC_GMACFLOWCONTROL_REG, EMAC_PAUSE_LOW_THRESHOLD, 0x1);
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}
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void emac_disable_flowctrl(void)
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{
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REG_CLR_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_TRANSMIT_FLOW_CONTROL_ENABLE);
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REG_CLR_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_RECEIVE_FLOW_CONTROL_ENABLE);
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REG_CLR_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_DISABLE_ZERO_QUANTA_PAUSE);
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REG_SET_FIELD(EMAC_GMACFLOWCONTROL_REG, EMAC_PAUSE_TIME, 0);
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REG_SET_FIELD(EMAC_GMACFLOWCONTROL_REG, EMAC_PAUSE_LOW_THRESHOLD, 0);
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}
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void emac_enable_dma_tx(void)
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{
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_TRANSMISSION_COMMAND);
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}
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void emac_enable_dma_rx(void)
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{
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_RECEIVE);
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}
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void emac_disable_dma_tx(void)
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{
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REG_CLR_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_OPERATE_SECOND_FRAME);
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}
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void emac_disable_dma_rx(void)
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{
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REG_CLR_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_RECEIVE);
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}
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uint32_t emac_read_mac_version(void)
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{
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uint32_t data = 0;
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data = REG_READ(EMAC_GMACVERSION_REG);
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return data;
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}
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void emac_reset(void)
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{
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REG_SET_BIT(EMAC_DMABUSMODE_REG, EMAC_SW_RST);
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while (REG_GET_BIT(EMAC_DMABUSMODE_REG, EMAC_SW_RST) == 1) {
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//nothing to do ,if stop here,maybe emac have not clk input.
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ESP_LOGI(TAG, "emac reseting ....");
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}
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ESP_LOGI(TAG, "emac reset done");
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}
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void emac_enable_clk(bool enable)
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{
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if (enable == true) {
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REG_SET_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
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} else {
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REG_CLR_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
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}
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}
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void emac_set_clk_mii(void)
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{
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//select ex clock source
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REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN);
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//ex clk enable
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REG_SET_BIT(EMAC_EX_OSCCLK_CONF_REG, EMAC_EX_OSC_CLK_SEL);
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//set mii mode rx/tx clk enable
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REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_MII_CLK_RX_EN);
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REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_MII_CLK_TX_EN);
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}
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void emac_dma_init(void)
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{
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_FORWARD_UNDERSIZED_GOOD_FRAMES);
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_OPERATE_SECOND_FRAME);
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REG_SET_FIELD(EMAC_DMABUSMODE_REG, EMAC_PROG_BURST_LEN, 4);
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_DMAOPERATION_MODE_REG);
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}
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void emac_mac_enable_txrx(void)
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{
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REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACRX);
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REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACTX);
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}
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void emac_mac_init(void)
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{
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REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACDUPLEX);
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REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACMIIGMII);
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REG_CLR_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACFESPEED);
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REG_SET_BIT(EMAC_GMACFRAMEFILTER_REG, EMAC_PROMISCUOUS_MODE);
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}
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void emac_set_clk_rmii(void)
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{
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//select ex clock source
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REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN);
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//ex clk enable
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REG_SET_BIT(EMAC_EX_OSCCLK_CONF_REG, EMAC_EX_OSC_CLK_SEL);
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}
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