512 lines
24 KiB
C
512 lines
24 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <rom/ets_sys.h>
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#include <freertos/heap_regions.h>
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#include "esp_heap_alloc_caps.h"
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#include "esp_psram.h"
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#include "esp_log.h"
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#include <stdbool.h>
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static const char* TAG = "heap_alloc_caps";
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/*
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This file, combined with a region allocator that supports tags, solves the problem that the ESP32 has RAM that's
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slightly heterogeneous. Some RAM can be byte-accessed, some allows only 32-bit accesses, some can execute memory,
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some can be remapped by the MMU to only be accessed by a certain PID etc. In order to allow the most flexible
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memory allocation possible, this code makes it possible to request memory that has certain capabilities. The
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code will then use its knowledge of how the memory is configured along with a priority scheme to allocate that
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memory in the most sane way possible. This should optimize the amount of RAM accessible to the code without
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hardwiring addresses.
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*/
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//Amount of priority slots for the tag descriptors.
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#define NO_PRIOS 3
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typedef struct {
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const char *name;
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uint32_t prio[NO_PRIOS];
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bool aliasedIram;
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} tag_desc_t;
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/*
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Tag descriptors. These describe the capabilities of a bit of memory that's tagged with the index into this table.
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Each tag contains NO_PRIOS entries; later entries are only taken if earlier ones can't fulfill the memory request.
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Make sure there are never more than HEAPREGIONS_MAX_TAGCOUNT (in heap_regions.h) tags (ex the last empty marker)
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WARNING: The current code assumes the ROM stacks are located in tag 1; no allocation from this tag can be done until
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the FreeRTOS scheduler has started.
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*/
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static const tag_desc_t tag_desc[]={
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{ "DRAM", { MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT, MALLOC_CAP_INTERNAL }, false}, //Tag 0: Plain ole D-port RAM
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{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC|MALLOC_CAP_INTERNAL }, true}, //Tag 1: Plain ole D-port RAM which has an alias on the I-port
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{ "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT, 0, MALLOC_CAP_INTERNAL }, false}, //Tag 2: IRAM
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{ "PID2IRAM", { MALLOC_CAP_PID2, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //Tag 3-8: PID 2-7 IRAM
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{ "PID3IRAM", { MALLOC_CAP_PID3, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID4IRAM", { MALLOC_CAP_PID4, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID5IRAM", { MALLOC_CAP_PID5, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID6IRAM", { MALLOC_CAP_PID6, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID7IRAM", { MALLOC_CAP_PID7, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID2DRAM", { MALLOC_CAP_PID2, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //Tag 9-14: PID 2-7 DRAM
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{ "PID3DRAM", { MALLOC_CAP_PID3, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID4DRAM", { MALLOC_CAP_PID4, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID5DRAM", { MALLOC_CAP_PID5, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID6DRAM", { MALLOC_CAP_PID6, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "PID7DRAM", { MALLOC_CAP_PID7, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL }, false}, //
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{ "SPIRAM", { MALLOC_CAP_SPIRAM, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false}, //Tag 15: SPI SRAM data
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{ "", { MALLOC_CAP_INVALID, MALLOC_CAP_INVALID, MALLOC_CAP_INVALID }, false} //End
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};
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/*
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Region descriptors. These describe all regions of memory available, and tag them according to the
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capabilities the hardware has. This array is not marked constant; the initialization code may want to
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change the tags of some regions because eg BT is detected, applications are loaded etc.
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The priorities here roughly work like this:
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- For a normal malloc (MALLOC_CAP_8BIT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions,
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finally eat into the application memory.
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- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
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- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
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- Most other malloc caps only fit in one region anyway.
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These region descriptors are very ESP32 specific, because they describe the memory pools available there.
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Because of requirements in the coalescing code as well as the heap allocator itself, this list should always
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be sorted from low to high start address.
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This array is *NOT* const because it gets modified depending on what pools are/aren't available.
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*/
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static HeapRegionTagged_t regions[]={
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{ (uint8_t *)0x3F800000, 0x400000, 15, 0}, //SPI SRAM, if available
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{ (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
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{ (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
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{ (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- if BT is enabled, used data memory for BT ROM functions.
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{ (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
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{ (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
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{ (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
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{ (uint8_t *)0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
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{ (uint8_t *)0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
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{ (uint8_t *)0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
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{ (uint8_t *)0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
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{ (uint8_t *)0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
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{ (uint8_t *)0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
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{ (uint8_t *)0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
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{ (uint8_t *)0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
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{ (uint8_t *)0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
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{ (uint8_t *)0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
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{ (uint8_t *)0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
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{ (uint8_t *)0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
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{ (uint8_t *)0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
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{ (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
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{ (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
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{ (uint8_t *)0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
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{ (uint8_t *)0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
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{ (uint8_t *)0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
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{ (uint8_t *)0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
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{ (uint8_t *)0x40070000, 0x8000, 2, 0}, //pool 0
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{ (uint8_t *)0x40078000, 0x8000, 2, 0}, //pool 1
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{ (uint8_t *)0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
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{ (uint8_t *)0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
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{ (uint8_t *)0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
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{ (uint8_t *)0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
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{ (uint8_t *)0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
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{ (uint8_t *)0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
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{ (uint8_t *)0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
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{ (uint8_t *)0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
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{ (uint8_t *)0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
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{ (uint8_t *)0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
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{ (uint8_t *)0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
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{ (uint8_t *)0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
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{ (uint8_t *)0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
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{ (uint8_t *)0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
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{ (uint8_t *)0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
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{ (uint8_t *)0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
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{ NULL, 0, 0, 0} //end
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};
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/* For the startup code, the stacks live in memory tagged by this tag. Hence, we only enable allocating from this tag
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once FreeRTOS has started up completely. */
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#define NONOS_STACK_TAG 1
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static bool nonos_stack_in_use=true;
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void heap_alloc_enable_nonos_stack_tag()
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{
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nonos_stack_in_use=false;
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}
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bool esp32_ptr_has_memory_caps(void *ptr, int caps) {
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int tag=-1;
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//Look up region tag of pointer
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for (int i=0; regions[i].xSizeInBytes!=0; i++) {
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if (regions[i].xTag != -1 &&
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(uint8_t*)ptr >= regions[i].pucStartAddress &&
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(uint8_t*)ptr < regions[i].pucStartAddress+regions[i].xSizeInBytes) {
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tag=regions[i].xTag;
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break;
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}
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}
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if (tag==-1) return false;
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//Mask off all the caps the tag does have. What should remain is the caps the tag does not have.
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for (int i=0; i<NO_PRIOS; i++) caps&=~(tag_desc[tag].prio[i]);
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//If any remain, ptr does not have all given caps.
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return (caps==0);
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}
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bool esp32_task_stack_is_internal() {
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int i;
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return esp32_ptr_has_memory_caps(&i, MALLOC_CAP_INTERNAL);
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}
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//Modify regions array to disable the given range of memory.
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static void disable_mem_region(void *from, void *to) {
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int i;
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//Align from and to on word boundaries
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from=(void*)((uint32_t)from&~3);
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to=(void*)(((uint32_t)to+3)&~3);
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for (i=0; regions[i].xSizeInBytes!=0; i++) {
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void *regStart=regions[i].pucStartAddress;
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void *regEnd=regions[i].pucStartAddress+regions[i].xSizeInBytes;
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if (regStart>=from && regEnd<=to) {
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//Entire region falls in the range. Disable entirely.
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regions[i].xTag=-1;
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} else if (regStart>=from && regEnd>to && regStart<to) {
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//Start of the region falls in the range. Modify address/len.
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int overlap=(uint8_t *)to-(uint8_t *)regStart;
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regions[i].pucStartAddress+=overlap;
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regions[i].xSizeInBytes-=overlap;
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if (regions[i].xExecAddr) regions[i].xExecAddr+=overlap;
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} else if (regStart<from && regEnd>from && regEnd<=to) {
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//End of the region falls in the range. Modify length.
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regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from;
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} else if (regStart<from && regEnd>to) {
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//Range punches a hole in the region! We do not support this.
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ESP_EARLY_LOGE(TAG, "region %d: hole punching is not supported!", i);
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regions[i].xTag=-1; //Just disable memory region. That'll teach them!
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}
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}
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}
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/*
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Warning: These variables are assumed to have the start and end of the data and iram
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area used statically by the program, respectively. These variables are defined in the ld
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file.
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*/
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extern int _data_start, _heap_start, _init_start, _iram_text_end;
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#if CONFIG_MEMMAP_SPIRAM_TEST
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/*
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Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
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true when RAM seems OK, false when test fails.
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*/
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static bool test_spiram(size_t s)
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{
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volatile int *spiram=(volatile int*)0x3F800000;
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size_t p;
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int errct=0;
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int initial_err=-1;
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for (p=0; p<s/4; p+=8) {
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spiram[p]=p^0xAAAAAAAA;
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}
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for (p=0; p<s/4; p+=8) {
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if (spiram[p]!=(p^0xAAAAAAAA)) {
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errct++;
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if (errct==1) initial_err=p*4;
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}
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}
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if (errct) {
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ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err+0x3F800000);
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return false;
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} else {
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ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
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return true;
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}
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}
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#endif
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/*
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Initialize the heap allocator. We pass it a bunch of region descriptors, but we need to modify those first to accommodate for
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the data as loaded by the bootloader.
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ToDo: The regions are different when stuff like trace memory, BT, ... is used. Modify the regions struct on the fly for this.
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Same with loading of apps. Same with using SPI RAM.
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*/
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void heap_alloc_caps_init() {
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int i;
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//Compile-time assert to see if we don't have more tags than is set in heap_regions.h
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_Static_assert((sizeof(tag_desc)/sizeof(tag_desc[0]))-1 <= HEAPREGIONS_MAX_TAGCOUNT, "More than HEAPREGIONS_MAX_TAGCOUNT tags defined!");
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//Disable the bits of memory where this code is loaded.
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disable_mem_region(&_data_start, &_heap_start); //DRAM used by bss/data static variables
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disable_mem_region(&_init_start, &_iram_text_end); //IRAM used by code
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disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region
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#ifdef CONFIG_MEMMAP_SMP
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disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region
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#endif
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/* Warning: The ROM stack is located in the 0x3ffe0000 area. We do not specifically disable that area here because
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after the scheduler has started, the ROM stack is not used anymore by anything. We handle it instead by not allowing
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any mallocs from tag 1 (the IRAM/DRAM region) until the scheduler has started.
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The 0x3ffe0000 region also contains static RAM for various ROM functions. The following lines
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reserve the regions for UART and ETSC, so these functions are usable. Libraries like xtos, which are
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not usable in FreeRTOS anyway, are commented out in the linker script so they cannot be used; we
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do not disable their memory regions here and they will be used as general purpose heap memory.
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Enabling the heap allocator for this region but disabling allocation here until FreeRTOS is started up
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is a somewhat risky action in theory, because on initializing the allocator, vPortDefineHeapRegionsTagged
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will go and write linked list entries at the start and end of all regions. For the ESP32, these linked
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list entries happen to end up in a region that is not touched by the stack; they can be placed safely there.*/
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disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe0440); //Reserve ROM PRO data region
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disable_mem_region((void*)0x3ffe4000, (void*)0x3ffe4350); //Reserve ROM APP data region
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#if CONFIG_BT_ENABLED
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#if CONFIG_BT_DRAM_RELEASE
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disable_mem_region((void*)0x3ffb0000, (void*)0x3ffb3000); //Reserve BT data region
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disable_mem_region((void*)0x3ffb8000, (void*)0x3ffbbb28); //Reserve BT data region
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disable_mem_region((void*)0x3ffbdb28, (void*)0x3ffc0000); //Reserve BT data region
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#else
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disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //Reserve BT hardware shared memory & BT data region
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#endif
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disable_mem_region((void*)0x3ffae000, (void*)0x3ffaff10); //Reserve ROM data region, inc region needed for BT ROM routines
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#else
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disable_mem_region((void*)0x3ffae000, (void*)0x3ffae2a0); //Reserve ROM data region
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#endif
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#if CONFIG_MEMMAP_TRACEMEM
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#if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
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disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //Reserve trace mem region
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#else
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disable_mem_region((void*)0x3fff8000, (void*)0x3fffc000); //Reserve trace mem region
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#endif
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#endif
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#if CONFIG_MEMMAP_SPIRAM_ENABLE && !CONFIG_MEMMAP_SPIRAM_NO_HEAPALLOC
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if (CONFIG_MEMMAP_SPIRAM_SIZE < 0x400000) {
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disable_mem_region((void*)0x3f800000+CONFIG_MEMMAP_SPIRAM_SIZE, (void*)0x3fc00000); //Disable unused SPI SRAM region
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}
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#if CONFIG_MEMMAP_SPIRAM_TEST
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if (!test_spiram(CONFIG_MEMMAP_SPIRAM_SIZE)) abort();
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#endif
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#else //!CONFIG_MEMMAP_SPIRAM_ENABLE
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disable_mem_region((void*)0x3f800000, (void*)0x3fc00000); //SPI SRAM not installed
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#endif
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//The heap allocator will treat every region given to it as separate. In order to get bigger ranges of contiguous memory,
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//it's useful to coalesce adjacent regions that have the same tag.
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for (i=1; regions[i].xSizeInBytes!=0; i++) {
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if (regions[i].pucStartAddress == (regions[i-1].pucStartAddress + regions[i-1].xSizeInBytes) &&
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regions[i].xTag == regions[i-1].xTag ) {
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regions[i-1].xTag=-1;
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regions[i].pucStartAddress=regions[i-1].pucStartAddress;
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regions[i].xSizeInBytes+=regions[i-1].xSizeInBytes;
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}
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}
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ESP_EARLY_LOGI(TAG, "Initializing. RAM available for dynamic allocation:");
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for (i=0; regions[i].xSizeInBytes!=0; i++) {
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if (regions[i].xTag != -1) {
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ESP_EARLY_LOGI(TAG, "At %08X len %08X (%d KiB): %s",
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(int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xSizeInBytes/1024, tag_desc[regions[i].xTag].name);
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}
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}
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//Initialize the malloc implementation.
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vPortDefineHeapRegionsTagged( regions );
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}
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//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
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#define DIRAM_IRAM_START 0x400A0000
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#define DIRAM_IRAM_END 0x400BFFFC
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#define DIRAM_DRAM_START 0x3FFE0000
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#define DIRAM_DRAM_END 0x3FFFFFFC
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/*
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This takes a memory chunk in a region that can be addressed as both DRAM as well as IRAM. It will convert it to
|
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IRAM in such a way that it can be later freed. It assumes both the address as wel as the length to be word-aligned.
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It returns a region that's 1 word smaller than the region given because it stores the original Dram address there.
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In theory, we can also make this work by prepending a struct that looks similar to the block link struct used by the
|
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heap allocator itself, which will allow inspection tools relying on any block returned from any sort of malloc to
|
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have such a block in front of it, work. We may do this later, if/when there is demand for it. For now, a simple
|
|
pointer is used.
|
|
*/
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static void *dram_alloc_to_iram_addr(void *addr, size_t len)
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|
{
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uint32_t dstart=(int)addr; //First word
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uint32_t dend=((int)addr)+len-4; //Last word
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configASSERT(dstart>=DIRAM_DRAM_START);
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configASSERT(dend<=DIRAM_DRAM_END);
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configASSERT((dstart&3)==0);
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configASSERT((dend&3)==0);
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uint32_t istart=DIRAM_IRAM_START+(DIRAM_DRAM_END-dend);
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uint32_t *iptr=(uint32_t*)istart;
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*iptr=dstart;
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return (void*)(iptr+1);
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}
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/*
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Standard malloc() implementation. Will return standard no-frills byte-accessible data memory.
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|
*/
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void *pvPortMalloc( size_t xWantedSize )
|
|
{
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|
#if CONFIG_MEMMAP_SPIRAM_ENABLE_MALLOC
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void *ret;
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if (xWantedSize > CONFIG_MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL) {
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ret = pvPortMallocCaps ( xWantedSize, MALLOC_CAP_8BIT|MALLOC_CAP_SPIRAM );
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} else {
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ret = pvPortMallocCaps ( xWantedSize, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL );
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}
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|
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if (ret == NULL) {
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//Preferred memory pool has too little space left. Fall back to just grabbing any 8bit-capable memory.
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ret = pvPortMallocCaps ( xWantedSize, MALLOC_CAP_8BIT );
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}
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return ret;
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#else
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//Only have internal memory. Just allocate there.
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return pvPortMallocCaps( xWantedSize, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL );
|
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#endif
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}
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|
|
/*
|
|
Standard free() implementation. Will pass memory on to the allocator unless it's an IRAM address where the
|
|
actual meory is allocated in DRAM, it will convert to the DRAM address then.
|
|
*/
|
|
void vPortFree( void *pv )
|
|
{
|
|
if (((int)pv>=DIRAM_IRAM_START) && ((int)pv<=DIRAM_IRAM_END)) {
|
|
//Memory allocated here is actually allocated in the DRAM alias region and
|
|
//cannot be de-allocated as usual. dram_alloc_to_iram_addr stores a pointer to
|
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//the equivalent DRAM address, though; free that.
|
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uint32_t* dramAddrPtr=(uint32_t*)pv;
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return vPortFreeTagged((void*)dramAddrPtr[-1]);
|
|
}
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|
|
return vPortFreeTagged(pv);
|
|
}
|
|
|
|
/*
|
|
Routine to allocate a bit of memory with certain capabilities. caps is a bitfield of MALLOC_CAP_* bits.
|
|
*/
|
|
void *pvPortMallocCaps( size_t xWantedSize, uint32_t caps )
|
|
{
|
|
int prio;
|
|
int tag, j;
|
|
void *ret=NULL;
|
|
uint32_t remCaps;
|
|
if (caps & MALLOC_CAP_EXEC) {
|
|
//MALLOC_CAP_EXEC forces an alloc from IRAM. There is a region which has both this
|
|
//as well as the following caps, but the following caps are not possible for IRAM.
|
|
//Thus, the combination is impossible and we return NULL directly, even although our tag_desc
|
|
//table would indicate there is a tag for this.
|
|
if ((caps & MALLOC_CAP_8BIT) || (caps & MALLOC_CAP_DMA)) {
|
|
return NULL;
|
|
}
|
|
//If any, EXEC memory should be 32-bit aligned, so round up to the next multiple of 4.
|
|
xWantedSize=(xWantedSize+3)&(~3);
|
|
}
|
|
for (prio=0; prio<NO_PRIOS; prio++) {
|
|
//Iterate over tag descriptors for this priority
|
|
for (tag=0; tag_desc[tag].prio[prio]!=MALLOC_CAP_INVALID; tag++) {
|
|
if (nonos_stack_in_use && tag == NONOS_STACK_TAG) {
|
|
//Non-os stack lives here and is still in use. Don't alloc here.
|
|
continue;
|
|
}
|
|
if ((tag_desc[tag].prio[prio]&caps)!=0) {
|
|
//Tag has at least one of the caps requested. If caps has other bits set that this prio
|
|
//doesn't cover, see if they're available in other prios.
|
|
remCaps=caps&(~tag_desc[tag].prio[prio]); //Remaining caps to be fulfilled
|
|
j=prio+1;
|
|
while (remCaps!=0 && j<NO_PRIOS) {
|
|
remCaps=remCaps&(~tag_desc[tag].prio[j]);
|
|
j++;
|
|
}
|
|
if (remCaps==0) {
|
|
//This tag can satisfy all the requested capabilities. See if we can grab some memory using it.
|
|
if ((caps & MALLOC_CAP_EXEC) && tag_desc[tag].aliasedIram) {
|
|
//This is special, insofar that what we're going to get back is probably a DRAM address. If so,
|
|
//we need to 'invert' it (lowest address in DRAM == highest address in IRAM and vice-versa) and
|
|
//add a pointer to the DRAM equivalent before the address we're going to return.
|
|
ret=pvPortMallocTagged(xWantedSize+4, tag);
|
|
if (ret!=NULL) return dram_alloc_to_iram_addr(ret, xWantedSize+4);
|
|
} else {
|
|
//Just try to alloc, nothing special.
|
|
ret=pvPortMallocTagged(xWantedSize, tag);
|
|
if (ret!=NULL) return ret;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
//Nothing usable found.
|
|
return NULL;
|
|
}
|
|
|
|
|
|
size_t xPortGetFreeHeapSizeCaps( uint32_t caps )
|
|
{
|
|
int prio;
|
|
int tag;
|
|
int cumTag;
|
|
size_t ret=0;
|
|
for (tag=0; tag_desc[tag].prio[0]!=MALLOC_CAP_INVALID; tag++) {
|
|
//Get tags for all priorities
|
|
cumTag=0;
|
|
for (prio=0; prio<NO_PRIOS; prio++) {
|
|
cumTag|=tag_desc[tag].prio[prio];
|
|
}
|
|
//Add to total if tag has all the capabilities in cap.
|
|
if ((cumTag&caps)==caps) {
|
|
ret+=xPortGetFreeHeapSizeTagged(tag);
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
size_t xPortGetMinimumEverFreeHeapSizeCaps( uint32_t caps )
|
|
{
|
|
int prio;
|
|
int tag;
|
|
int cumTag;
|
|
size_t ret=0;
|
|
for (tag=0; tag_desc[tag].prio[0]!=MALLOC_CAP_INVALID; tag++) {
|
|
//Get tags for all priorities
|
|
cumTag=0;
|
|
for (prio=0; prio<NO_PRIOS; prio++) {
|
|
cumTag|=tag_desc[tag].prio[prio];
|
|
}
|
|
//Add to total if tag has all the capabilities in cap.
|
|
if ((cumTag&caps)==caps) {
|
|
ret+=xPortGetMinimumEverFreeHeapSizeTagged(tag);
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
size_t xPortGetFreeHeapSize( void )
|
|
{
|
|
return xPortGetFreeHeapSizeCaps( MALLOC_CAP_8BIT );
|
|
}
|
|
|
|
size_t xPortGetMinimumEverFreeHeapSize( void )
|
|
{
|
|
return xPortGetMinimumEverFreeHeapSizeCaps( MALLOC_CAP_8BIT );
|
|
}
|
|
|
|
|