5a88f90a33
Since 9a8c0392, XTAL frequency is set to 40MHz by default, and users
of 26MHz boards need to select 26MHz manually. Most users are not aware
of this change, and existing getting started guides do not mention that
XTAL frequency needs to be set for some boards. So users are left with
garbage output from UART without any clue what to check.
This change adds a warning in case specific XTAL frequency was set, and
it does not match automatically detected one. This should help users
fix the issue.
902 lines
32 KiB
C
902 lines
32 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include <stdint.h>
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#include <limits.h>
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#include <sys/param.h>
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "rom/cache.h"
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#include "rom/efuse.h"
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#include "rom/ets_sys.h"
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#include "rom/spi_flash.h"
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#include "rom/crc.h"
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#include "rom/rtc.h"
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#include "rom/uart.h"
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#include "rom/gpio.h"
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#include "rom/secure_boot.h"
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#include "soc/soc.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timer_group_reg.h"
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#include "soc/gpio_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "sdkconfig.h"
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#include "esp_image_format.h"
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#include "esp_secure_boot.h"
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#include "esp_flash_encrypt.h"
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#include "esp_flash_partitions.h"
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#include "bootloader_flash.h"
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#include "bootloader_random.h"
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#include "bootloader_config.h"
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#include "flash_qio_mode.h"
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extern int _bss_start;
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extern int _bss_end;
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extern int _data_start;
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extern int _data_end;
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static const char* TAG = "boot";
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/* Reduce literal size for some generic string literals */
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#define MAP_MSG "Mapping segment %d as %s"
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#define MAP_ERR_MSG "Image contains multiple %s segments. Only the last one will be mapped."
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void bootloader_main();
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static void unpack_load_app(const esp_image_metadata_t *data);
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static void print_flash_info(const esp_image_header_t* pfhdr);
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static void set_cache_and_start_app(uint32_t drom_addr,
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uint32_t drom_load_addr,
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uint32_t drom_size,
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uint32_t irom_addr,
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uint32_t irom_load_addr,
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uint32_t irom_size,
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uint32_t entry_addr);
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static void update_flash_config(const esp_image_header_t* pfhdr);
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static void clock_configure(void);
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static void uart_console_configure(void);
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static void wdt_reset_check(void);
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/*
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* We arrive here after the ROM bootloader finished loading this second stage bootloader from flash.
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* The hardware is mostly uninitialized, flash cache is down and the app CPU is in reset.
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* We do have a stack, so we can do the initialization in C.
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*/
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void call_start_cpu0()
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{
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cpu_configure_region_protection();
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/* Sanity check that static RAM is after the stack */
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#ifndef NDEBUG
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{
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int *sp = get_sp();
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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assert(sp < &_bss_start);
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assert(sp < &_data_start);
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}
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#endif
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//Clear bss
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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/* completely reset MMU for both CPUs
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(in case serial bootloader was running) */
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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Cache_Flush(0);
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Cache_Flush(1);
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mmu_init(0);
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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mmu_init(1);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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/* (above steps probably unnecessary for most serial bootloader
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usage, all that's absolutely needed is that we unmask DROM0
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cache on the following two lines - normal ROM boot exits with
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DROM0 cache unmasked, but serial bootloader exits with it
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masked. However can't hurt to be thorough and reset
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everything.)
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The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
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necessary to work around a hardware bug.
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*/
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
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bootloader_main();
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}
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/** @brief Load partition table
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*
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* Parse partition table, get useful data such as location of
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* OTA data partition, factory app partition, and test app partition.
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*
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* @param bs bootloader state structure used to save read data
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* @return return true if the partition table was succesfully loaded and MD5 checksum is valid.
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*/
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bool load_partition_table(bootloader_state_t* bs)
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{
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const esp_partition_info_t *partitions;
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const int ESP_PARTITION_TABLE_DATA_LEN = 0xC00; /* length of actual data (signature is appended to this) */
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char *partition_usage;
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esp_err_t err;
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int num_partitions;
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#ifdef CONFIG_SECURE_BOOT_ENABLED
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if(esp_secure_boot_enabled()) {
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ESP_LOGI(TAG, "Verifying partition table signature...");
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err = esp_secure_boot_verify_signature(ESP_PARTITION_TABLE_ADDR, ESP_PARTITION_TABLE_DATA_LEN);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "Failed to verify partition table signature.");
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return false;
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}
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ESP_LOGD(TAG, "Partition table signature verified");
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}
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#endif
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partitions = bootloader_mmap(ESP_PARTITION_TABLE_ADDR, ESP_PARTITION_TABLE_DATA_LEN);
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if (!partitions) {
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ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", ESP_PARTITION_TABLE_ADDR, ESP_PARTITION_TABLE_DATA_LEN);
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return false;
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}
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ESP_LOGD(TAG, "mapped partition table 0x%x at 0x%x", ESP_PARTITION_TABLE_ADDR, (intptr_t)partitions);
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err = esp_partition_table_basic_verify(partitions, true, &num_partitions);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "Failed to verify partition table");
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return false;
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}
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ESP_LOGI(TAG, "Partition Table:");
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ESP_LOGI(TAG, "## Label Usage Type ST Offset Length");
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for(int i = 0; i < num_partitions; i++) {
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const esp_partition_info_t *partition = &partitions[i];
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ESP_LOGD(TAG, "load partition table entry 0x%x", (intptr_t)partition);
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ESP_LOGD(TAG, "type=%x subtype=%x", partition->type, partition->subtype);
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partition_usage = "unknown";
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/* valid partition table */
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switch(partition->type) {
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case PART_TYPE_APP: /* app partition */
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switch(partition->subtype) {
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case PART_SUBTYPE_FACTORY: /* factory binary */
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bs->factory = partition->pos;
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partition_usage = "factory app";
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break;
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case PART_SUBTYPE_TEST: /* test binary */
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bs->test = partition->pos;
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partition_usage = "test app";
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break;
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default:
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/* OTA binary */
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if ((partition->subtype & ~PART_SUBTYPE_OTA_MASK) == PART_SUBTYPE_OTA_FLAG) {
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bs->ota[partition->subtype & PART_SUBTYPE_OTA_MASK] = partition->pos;
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++bs->app_count;
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partition_usage = "OTA app";
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}
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else {
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partition_usage = "Unknown app";
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}
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break;
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}
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break; /* PART_TYPE_APP */
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case PART_TYPE_DATA: /* data partition */
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switch(partition->subtype) {
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case PART_SUBTYPE_DATA_OTA: /* ota data */
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bs->ota_info = partition->pos;
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partition_usage = "OTA data";
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break;
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case PART_SUBTYPE_DATA_RF:
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partition_usage = "RF data";
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break;
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case PART_SUBTYPE_DATA_WIFI:
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partition_usage = "WiFi data";
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break;
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default:
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partition_usage = "Unknown data";
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break;
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}
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break; /* PARTITION_USAGE_DATA */
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default: /* other partition type */
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break;
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}
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/* print partition type info */
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ESP_LOGI(TAG, "%2d %-16s %-16s %02x %02x %08x %08x", i, partition->label, partition_usage,
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partition->type, partition->subtype,
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partition->pos.offset, partition->pos.size);
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}
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bootloader_munmap(partitions);
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ESP_LOGI(TAG,"End of partition table");
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return true;
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}
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static uint32_t ota_select_crc(const esp_ota_select_entry_t *s)
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{
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return crc32_le(UINT32_MAX, (uint8_t*)&s->ota_seq, 4);
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}
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static bool ota_select_valid(const esp_ota_select_entry_t *s)
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{
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return s->ota_seq != UINT32_MAX && s->crc == ota_select_crc(s);
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}
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/* indexes used by index_to_partition are the OTA index
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number, or these special constants */
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#define FACTORY_INDEX (-1)
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#define TEST_APP_INDEX (-2)
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#define INVALID_INDEX (-99)
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/* Given a partition index, return the partition position data from the bootloader_state_t structure */
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static esp_partition_pos_t index_to_partition(const bootloader_state_t *bs, int index)
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{
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if (index == FACTORY_INDEX) {
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return bs->factory;
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}
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if (index == TEST_APP_INDEX) {
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return bs->test;
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}
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if (index >= 0 && index < MAX_OTA_SLOTS && index < bs->app_count) {
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return bs->ota[index];
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}
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esp_partition_pos_t invalid = { 0 };
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return invalid;
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}
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static void log_invalid_app_partition(int index)
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{
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const char *not_bootable = " is not bootable"; /* save a few string literal bytes */
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switch(index) {
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case FACTORY_INDEX:
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ESP_LOGE(TAG, "Factory app partition%s", not_bootable);
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break;
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case TEST_APP_INDEX:
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ESP_LOGE(TAG, "Factory test app partition%s", not_bootable);
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break;
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default:
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ESP_LOGE(TAG, "OTA app partition slot %d%s", index, not_bootable);
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break;
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}
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}
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/* Return the index of the selected boot partition.
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This is the preferred boot partition, as determined by the partition table &
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any OTA sequence number found in OTA data.
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This partition will only be booted if it contains a valid app image, otherwise load_boot_image() will search
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for a valid partition using this selection as the starting point.
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*/
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static int get_selected_boot_partition(const bootloader_state_t *bs)
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{
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esp_ota_select_entry_t sa,sb;
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const esp_ota_select_entry_t *ota_select_map;
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if (bs->ota_info.offset != 0) {
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// partition table has OTA data partition
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if (bs->ota_info.size < 2 * SPI_SEC_SIZE) {
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ESP_LOGE(TAG, "ota_info partition size %d is too small (minimum %d bytes)", bs->ota_info.size, sizeof(esp_ota_select_entry_t));
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return INVALID_INDEX; // can't proceed
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}
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ESP_LOGD(TAG, "OTA data offset 0x%x", bs->ota_info.offset);
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ota_select_map = bootloader_mmap(bs->ota_info.offset, bs->ota_info.size);
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if (!ota_select_map) {
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ESP_LOGE(TAG, "bootloader_mmap(0x%x, 0x%x) failed", bs->ota_info.offset, bs->ota_info.size);
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return INVALID_INDEX; // can't proceed
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}
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memcpy(&sa, ota_select_map, sizeof(esp_ota_select_entry_t));
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memcpy(&sb, (uint8_t *)ota_select_map + SPI_SEC_SIZE, sizeof(esp_ota_select_entry_t));
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bootloader_munmap(ota_select_map);
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ESP_LOGD(TAG, "OTA sequence values A 0x%08x B 0x%08x", sa.ota_seq, sb.ota_seq);
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if(sa.ota_seq == UINT32_MAX && sb.ota_seq == UINT32_MAX) {
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ESP_LOGD(TAG, "OTA sequence numbers both empty (all-0xFF)");
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if (bs->factory.offset != 0) {
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ESP_LOGI(TAG, "Defaulting to factory image");
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return FACTORY_INDEX;
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} else {
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ESP_LOGI(TAG, "No factory image, trying OTA 0");
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return 0;
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}
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} else {
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bool ota_valid = false;
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const char *ota_msg;
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int ota_seq; // Raw OTA sequence number. May be more than # of OTA slots
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if(ota_select_valid(&sa) && ota_select_valid(&sb)) {
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ota_valid = true;
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ota_msg = "Both OTA values";
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ota_seq = MAX(sa.ota_seq, sb.ota_seq) - 1;
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} else if(ota_select_valid(&sa)) {
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ota_valid = true;
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ota_msg = "Only OTA sequence A is";
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ota_seq = sa.ota_seq - 1;
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} else if(ota_select_valid(&sb)) {
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ota_valid = true;
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ota_msg = "Only OTA sequence B is";
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ota_seq = sb.ota_seq - 1;
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}
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if (ota_valid) {
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int ota_slot = ota_seq % bs->app_count; // Actual OTA partition selection
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ESP_LOGD(TAG, "%s valid. Mapping seq %d -> OTA slot %d", ota_msg, ota_seq, ota_slot);
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return ota_slot;
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} else if (bs->factory.offset != 0) {
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ESP_LOGE(TAG, "ota data partition invalid, falling back to factory");
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return FACTORY_INDEX;
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} else {
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ESP_LOGE(TAG, "ota data partition invalid and no factory, will try all partitions");
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return FACTORY_INDEX;
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}
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}
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}
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// otherwise, start from factory app partition and let the search logic
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// proceed from there
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return FACTORY_INDEX;
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}
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/* Return true if a partition has a valid app image that was successfully loaded */
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static bool try_load_partition(const esp_partition_pos_t *partition, esp_image_metadata_t *data)
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{
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if (partition->size == 0) {
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ESP_LOGD(TAG, "Can't boot from zero-length partition");
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return false;
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}
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if (esp_image_load(ESP_IMAGE_LOAD, partition, data) == ESP_OK) {
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ESP_LOGI(TAG, "Loaded app from partition at offset 0x%x",
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partition->offset);
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return true;
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}
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return false;
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}
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#define TRY_LOG_FORMAT "Trying partition index %d offs 0x%x size 0x%x"
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/* Load the app for booting. Start from partition 'start_index', if not bootable then work backwards to FACTORY_INDEX
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* (ie try any OTA slots in descending order and then the factory partition).
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*
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* If still nothing, start from 'start_index + 1' and work up to highest numbered OTA partition.
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*
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* If still nothing, try TEST_APP_INDEX
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*
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* Returns true on success, false if there's no bootable app in the partition table.
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*/
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static bool load_boot_image(const bootloader_state_t *bs, int start_index, esp_image_metadata_t *result)
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{
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int index = start_index;
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esp_partition_pos_t part;
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/* work backwards from start_index, down to the factory app */
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for(index = start_index; index >= FACTORY_INDEX; index--) {
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part = index_to_partition(bs, index);
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if (part.size == 0) {
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continue;
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}
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ESP_LOGD(TAG, TRY_LOG_FORMAT, index, part.offset, part.size);
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if (try_load_partition(&part, result)) {
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return true;
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}
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log_invalid_app_partition(index);
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}
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/* failing that work forwards from start_index, try valid OTA slots */
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for(index = start_index + 1; index < bs->app_count; index++) {
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part = index_to_partition(bs, index);
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if (part.size == 0) {
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continue;
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}
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ESP_LOGD(TAG, TRY_LOG_FORMAT, index, part.offset, part.size);
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if (try_load_partition(&part, result)) {
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return true;
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}
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log_invalid_app_partition(index);
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}
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if (try_load_partition(&bs->test, result)) {
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ESP_LOGW(TAG, "Falling back to test app as only bootable partition");
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return true;
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}
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ESP_LOGE(TAG, "No bootable app partitions in the partition table");
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bzero(result, sizeof(esp_image_metadata_t));
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return false;
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}
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/**
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* @function : bootloader_main
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* @description: entry function of 2nd bootloader
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*
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* @inputs: void
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*/
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void bootloader_main()
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{
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clock_configure();
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uart_console_configure();
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wdt_reset_check();
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ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER);
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#if defined(CONFIG_SECURE_BOOT_ENABLED) || defined(CONFIG_FLASH_ENCRYPTION_ENABLED)
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esp_err_t err;
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#endif
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esp_image_header_t fhdr;
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bootloader_state_t bs = { 0 };
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ESP_LOGI(TAG, "compile time " __TIME__ );
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ets_set_appcpu_boot_addr(0);
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/* disable watch dog here */
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REG_CLR_BIT( RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
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REG_CLR_BIT( TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN );
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#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
|
|
if(spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
|
|
ESP_LOGE(TAG, "SPI flash pins are overridden. \"Enable SPI flash ROM driver patched functions\" must be enabled in menuconfig");
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
esp_rom_spiflash_unlock();
|
|
|
|
ESP_LOGI(TAG, "Enabling RNG early entropy source...");
|
|
bootloader_random_enable();
|
|
|
|
#if CONFIG_FLASHMODE_QIO || CONFIG_FLASHMODE_QOUT
|
|
bootloader_enable_qio_mode();
|
|
#endif
|
|
|
|
if (bootloader_flash_read(ESP_BOOTLOADER_OFFSET, &fhdr,
|
|
sizeof(esp_image_header_t), true) != ESP_OK) {
|
|
ESP_LOGE(TAG, "failed to load bootloader header!");
|
|
return;
|
|
}
|
|
|
|
print_flash_info(&fhdr);
|
|
|
|
update_flash_config(&fhdr);
|
|
|
|
if (!load_partition_table(&bs)) {
|
|
ESP_LOGE(TAG, "load partition table error!");
|
|
return;
|
|
}
|
|
|
|
int boot_index = get_selected_boot_partition(&bs);
|
|
if (boot_index == INVALID_INDEX) {
|
|
return; // Unrecoverable failure (not due to corrupt ota data or bad partition contents)
|
|
}
|
|
// Start from the default, look for the first bootable partition
|
|
esp_image_metadata_t image_data;
|
|
if (!load_boot_image(&bs, boot_index, &image_data)) {
|
|
return;
|
|
}
|
|
|
|
#ifdef CONFIG_SECURE_BOOT_ENABLED
|
|
/* Generate secure digest from this bootloader to protect future
|
|
modifications */
|
|
ESP_LOGI(TAG, "Checking secure boot...");
|
|
err = esp_secure_boot_permanently_enable();
|
|
if (err != ESP_OK) {
|
|
ESP_LOGE(TAG, "Bootloader digest generation failed (%d). SECURE BOOT IS NOT ENABLED.", err);
|
|
/* Allow booting to continue, as the failure is probably
|
|
due to user-configured EFUSEs for testing...
|
|
*/
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FLASH_ENCRYPTION_ENABLED
|
|
/* encrypt flash */
|
|
ESP_LOGI(TAG, "Checking flash encryption...");
|
|
bool flash_encryption_enabled = esp_flash_encryption_enabled();
|
|
err = esp_flash_encrypt_check_and_update();
|
|
if (err != ESP_OK) {
|
|
ESP_LOGE(TAG, "Flash encryption check failed (%d).", err);
|
|
return;
|
|
}
|
|
|
|
if (!flash_encryption_enabled && esp_flash_encryption_enabled()) {
|
|
/* Flash encryption was just enabled for the first time,
|
|
so issue a system reset to ensure flash encryption
|
|
cache resets properly */
|
|
ESP_LOGI(TAG, "Resetting with flash encryption enabled...");
|
|
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
ESP_LOGI(TAG, "Disabling RNG early entropy source...");
|
|
bootloader_random_disable();
|
|
|
|
// copy loaded segments to RAM, set up caches for mapped segments, and start application
|
|
unpack_load_app(&image_data);
|
|
}
|
|
|
|
static void unpack_load_app(const esp_image_metadata_t* data)
|
|
{
|
|
uint32_t drom_addr = 0;
|
|
uint32_t drom_load_addr = 0;
|
|
uint32_t drom_size = 0;
|
|
uint32_t irom_addr = 0;
|
|
uint32_t irom_load_addr = 0;
|
|
uint32_t irom_size = 0;
|
|
|
|
// Find DROM & IROM addresses, to configure cache mappings
|
|
for (int i = 0; i < data->image.segment_count; i++) {
|
|
const esp_image_segment_header_t *header = &data->segments[i];
|
|
if (header->load_addr >= SOC_IROM_LOW && header->load_addr < SOC_IROM_HIGH) {
|
|
if (drom_addr != 0) {
|
|
ESP_LOGE(TAG, MAP_ERR_MSG, "DROM");
|
|
} else {
|
|
ESP_LOGD(TAG, "Mapping segment %d as %s", i, "DROM");
|
|
}
|
|
drom_addr = data->segment_data[i];
|
|
drom_load_addr = header->load_addr;
|
|
drom_size = header->data_len;
|
|
}
|
|
if (header->load_addr >= SOC_DROM_LOW && header->load_addr < SOC_DROM_HIGH) {
|
|
if (irom_addr != 0) {
|
|
ESP_LOGE(TAG, MAP_ERR_MSG, "IROM");
|
|
} else {
|
|
ESP_LOGD(TAG, "Mapping segment %d as %s", i, "IROM");
|
|
}
|
|
irom_addr = data->segment_data[i];
|
|
irom_load_addr = header->load_addr;
|
|
irom_size = header->data_len;
|
|
}
|
|
}
|
|
|
|
ESP_LOGD(TAG, "calling set_cache_and_start_app");
|
|
set_cache_and_start_app(drom_addr,
|
|
drom_load_addr,
|
|
drom_size,
|
|
irom_addr,
|
|
irom_load_addr,
|
|
irom_size,
|
|
data->image.entry_addr);
|
|
}
|
|
|
|
static void set_cache_and_start_app(
|
|
uint32_t drom_addr,
|
|
uint32_t drom_load_addr,
|
|
uint32_t drom_size,
|
|
uint32_t irom_addr,
|
|
uint32_t irom_load_addr,
|
|
uint32_t irom_size,
|
|
uint32_t entry_addr)
|
|
{
|
|
ESP_LOGD(TAG, "configure drom and irom and start");
|
|
Cache_Read_Disable( 0 );
|
|
Cache_Flush( 0 );
|
|
|
|
/* Clear the MMU entries that are already set up,
|
|
so the new app only has the mappings it creates.
|
|
*/
|
|
for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++) {
|
|
DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
|
|
}
|
|
|
|
uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k
|
|
ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count );
|
|
int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
|
|
ESP_LOGV(TAG, "rc=%d", rc );
|
|
rc = cache_flash_mmu_set( 1, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
|
|
ESP_LOGV(TAG, "rc=%d", rc );
|
|
uint32_t irom_page_count = (irom_size + 64*1024 - 1) / (64*1024); // round up to 64k
|
|
ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count );
|
|
rc = cache_flash_mmu_set( 0, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
|
|
ESP_LOGV(TAG, "rc=%d", rc );
|
|
rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
|
|
ESP_LOGV(TAG, "rc=%d", rc );
|
|
DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
|
|
DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
|
|
Cache_Read_Enable( 0 );
|
|
|
|
// Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
|
|
|
|
ESP_LOGD(TAG, "start: 0x%08x", entry_addr);
|
|
typedef void (*entry_t)(void);
|
|
entry_t entry = ((entry_t) entry_addr);
|
|
|
|
// TODO: we have used quite a bit of stack at this point.
|
|
// use "movsp" instruction to reset stack back to where ROM stack starts.
|
|
(*entry)();
|
|
}
|
|
|
|
static void update_flash_config(const esp_image_header_t* pfhdr)
|
|
{
|
|
uint32_t size;
|
|
switch(pfhdr->spi_size) {
|
|
case ESP_IMAGE_FLASH_SIZE_1MB:
|
|
size = 1;
|
|
break;
|
|
case ESP_IMAGE_FLASH_SIZE_2MB:
|
|
size = 2;
|
|
break;
|
|
case ESP_IMAGE_FLASH_SIZE_4MB:
|
|
size = 4;
|
|
break;
|
|
case ESP_IMAGE_FLASH_SIZE_8MB:
|
|
size = 8;
|
|
break;
|
|
case ESP_IMAGE_FLASH_SIZE_16MB:
|
|
size = 16;
|
|
break;
|
|
default:
|
|
size = 2;
|
|
}
|
|
Cache_Read_Disable( 0 );
|
|
// Set flash chip size
|
|
esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
|
|
// TODO: set mode
|
|
// TODO: set frequency
|
|
Cache_Flush(0);
|
|
Cache_Read_Enable( 0 );
|
|
}
|
|
|
|
static void print_flash_info(const esp_image_header_t* phdr)
|
|
{
|
|
#if (BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_NOTICE)
|
|
|
|
ESP_LOGD(TAG, "magic %02x", phdr->magic );
|
|
ESP_LOGD(TAG, "segments %02x", phdr->segment_count );
|
|
ESP_LOGD(TAG, "spi_mode %02x", phdr->spi_mode );
|
|
ESP_LOGD(TAG, "spi_speed %02x", phdr->spi_speed );
|
|
ESP_LOGD(TAG, "spi_size %02x", phdr->spi_size );
|
|
|
|
const char* str;
|
|
switch ( phdr->spi_speed ) {
|
|
case ESP_IMAGE_SPI_SPEED_40M:
|
|
str = "40MHz";
|
|
break;
|
|
case ESP_IMAGE_SPI_SPEED_26M:
|
|
str = "26.7MHz";
|
|
break;
|
|
case ESP_IMAGE_SPI_SPEED_20M:
|
|
str = "20MHz";
|
|
break;
|
|
case ESP_IMAGE_SPI_SPEED_80M:
|
|
str = "80MHz";
|
|
break;
|
|
default:
|
|
str = "20MHz";
|
|
break;
|
|
}
|
|
ESP_LOGI(TAG, "SPI Speed : %s", str );
|
|
|
|
/* SPI mode could have been set to QIO during boot already,
|
|
so test the SPI registers not the flash header */
|
|
uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
|
|
if (spi_ctrl & SPI_FREAD_QIO) {
|
|
str = "QIO";
|
|
} else if (spi_ctrl & SPI_FREAD_QUAD) {
|
|
str = "QOUT";
|
|
} else if (spi_ctrl & SPI_FREAD_DIO) {
|
|
str = "DIO";
|
|
} else if (spi_ctrl & SPI_FREAD_DUAL) {
|
|
str = "DOUT";
|
|
} else if (spi_ctrl & SPI_FASTRD_MODE) {
|
|
str = "FAST READ";
|
|
} else {
|
|
str = "SLOW READ";
|
|
}
|
|
ESP_LOGI(TAG, "SPI Mode : %s", str );
|
|
|
|
switch ( phdr->spi_size ) {
|
|
case ESP_IMAGE_FLASH_SIZE_1MB:
|
|
str = "1MB";
|
|
break;
|
|
case ESP_IMAGE_FLASH_SIZE_2MB:
|
|
str = "2MB";
|
|
break;
|
|
case ESP_IMAGE_FLASH_SIZE_4MB:
|
|
str = "4MB";
|
|
break;
|
|
case ESP_IMAGE_FLASH_SIZE_8MB:
|
|
str = "8MB";
|
|
break;
|
|
case ESP_IMAGE_FLASH_SIZE_16MB:
|
|
str = "16MB";
|
|
break;
|
|
default:
|
|
str = "2MB";
|
|
break;
|
|
}
|
|
ESP_LOGI(TAG, "SPI Flash Size : %s", str );
|
|
#endif
|
|
}
|
|
|
|
|
|
static void clock_configure(void)
|
|
{
|
|
/* Set CPU to 80MHz. Keep other clocks unmodified. */
|
|
rtc_cpu_freq_t cpu_freq = RTC_CPU_FREQ_80M;
|
|
|
|
/* On ESP32 rev 0, switching to 80MHz if clock was previously set to
|
|
* 240 MHz may cause the chip to lock up (see section 3.5 of the errata
|
|
* document). For rev. 0, switch to 240 instead if it was chosen in
|
|
* menuconfig.
|
|
*/
|
|
uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
|
|
if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
|
|
CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240) {
|
|
cpu_freq = RTC_CPU_FREQ_240M;
|
|
}
|
|
|
|
rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
|
|
clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
|
|
clk_cfg.cpu_freq = cpu_freq;
|
|
clk_cfg.slow_freq = rtc_clk_slow_freq_get();
|
|
clk_cfg.fast_freq = rtc_clk_fast_freq_get();
|
|
rtc_clk_init(clk_cfg);
|
|
/* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
|
|
* it here. Usually it needs some time to start up, so we amortize at least
|
|
* part of the start up time by enabling 32k XTAL early.
|
|
* App startup code will wait until the oscillator has started up.
|
|
*/
|
|
#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
|
|
if (!rtc_clk_32k_enabled()) {
|
|
rtc_clk_32k_bootstrap();
|
|
}
|
|
#endif
|
|
}
|
|
|
|
static void uart_console_configure(void)
|
|
{
|
|
#if CONFIG_CONSOLE_UART_NONE
|
|
ets_install_putc1(NULL);
|
|
ets_install_putc2(NULL);
|
|
#else // CONFIG_CONSOLE_UART_NONE
|
|
const int uart_num = CONFIG_CONSOLE_UART_NUM;
|
|
|
|
uartAttach();
|
|
ets_install_uart_printf();
|
|
|
|
// ROM bootloader may have put a lot of text into UART0 FIFO.
|
|
// Wait for it to be printed.
|
|
uart_tx_wait_idle(0);
|
|
|
|
#if CONFIG_CONSOLE_UART_CUSTOM
|
|
// Some constants to make the following code less upper-case
|
|
const int uart_tx_gpio = CONFIG_CONSOLE_UART_TX_GPIO;
|
|
const int uart_rx_gpio = CONFIG_CONSOLE_UART_RX_GPIO;
|
|
// Switch to the new UART (this just changes UART number used for
|
|
// ets_printf in ROM code).
|
|
uart_tx_switch(uart_num);
|
|
// If console is attached to UART1 or if non-default pins are used,
|
|
// need to reconfigure pins using GPIO matrix
|
|
if (uart_num != 0 || uart_tx_gpio != 1 || uart_rx_gpio != 3) {
|
|
// Change pin mode for GPIO1/3 from UART to GPIO
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_GPIO3);
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_GPIO1);
|
|
// Route GPIO signals to/from pins
|
|
// (arrays should be optimized away by the compiler)
|
|
const uint32_t tx_idx_list[3] = { U0TXD_OUT_IDX, U1TXD_OUT_IDX, U2TXD_OUT_IDX };
|
|
const uint32_t rx_idx_list[3] = { U0RXD_IN_IDX, U1RXD_IN_IDX, U2RXD_IN_IDX };
|
|
const uint32_t tx_idx = tx_idx_list[uart_num];
|
|
const uint32_t rx_idx = rx_idx_list[uart_num];
|
|
gpio_matrix_out(uart_tx_gpio, tx_idx, 0, 0);
|
|
gpio_matrix_in(uart_rx_gpio, rx_idx, 0);
|
|
}
|
|
#endif // CONFIG_CONSOLE_UART_CUSTOM
|
|
|
|
// Set configured UART console baud rate
|
|
const int uart_baud = CONFIG_CONSOLE_UART_BAUDRATE;
|
|
uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
|
|
|
|
#endif // CONFIG_CONSOLE_UART_NONE
|
|
}
|
|
|
|
static void wdt_reset_cpu0_info_enable(void)
|
|
{
|
|
//We do not reset core1 info here because it didn't work before cpu1 was up. So we put it into call_start_cpu1.
|
|
DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE);
|
|
DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
|
|
}
|
|
|
|
static void wdt_reset_info_dump(int cpu)
|
|
{
|
|
uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
|
|
lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
|
|
char *cpu_name = cpu ? "APP" : "PRO";
|
|
|
|
if (cpu == 0) {
|
|
stat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_STATUS_REG);
|
|
pid = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PID_REG);
|
|
inst = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGINST_REG);
|
|
dstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG);
|
|
data = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG);
|
|
pc = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGPC_REG);
|
|
lsstat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG);
|
|
lsaddr = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG);
|
|
lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
|
|
|
|
} else {
|
|
stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
|
|
pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
|
|
inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
|
|
dstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG);
|
|
data = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGDATA_REG);
|
|
pc = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGPC_REG);
|
|
lsstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG);
|
|
lsaddr = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG);
|
|
lsdata = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG);
|
|
}
|
|
if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
|
|
DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
|
|
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x (waiti mode)", cpu_name, pc);
|
|
} else {
|
|
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x", cpu_name, pc);
|
|
}
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS 0x%08x", cpu_name, stat);
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU PID 0x%08x", cpu_name, pid);
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST 0x%08x", cpu_name, inst);
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS 0x%08x", cpu_name, dstat);
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA 0x%08x", cpu_name, data);
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC 0x%08x", cpu_name, pc);
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08x", cpu_name, lsstat);
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08x", cpu_name, lsaddr);
|
|
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08x", cpu_name, lsdata);
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|
}
|
|
|
|
static void wdt_reset_check(void)
|
|
{
|
|
int wdt_rst = 0;
|
|
RESET_REASON rst_reas[2];
|
|
|
|
rst_reas[0] = rtc_get_reset_reason(0);
|
|
rst_reas[1] = rtc_get_reset_reason(1);
|
|
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
|
|
rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
|
|
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
|
wdt_rst = 1;
|
|
}
|
|
if (rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET || rst_reas[1] == TG1WDT_SYS_RESET ||
|
|
rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET) {
|
|
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
|
|
wdt_rst = 1;
|
|
}
|
|
if (wdt_rst) {
|
|
// if reset by WDT dump info from trace port
|
|
wdt_reset_info_dump(0);
|
|
wdt_reset_info_dump(1);
|
|
}
|
|
wdt_reset_cpu0_info_enable();
|
|
}
|
|
|
|
void __assert_func(const char *file, int line, const char *func, const char *expr)
|
|
{
|
|
ESP_LOGE(TAG, "Assert failed in %s, %s:%d (%s)", func, file, line, expr);
|
|
while(1) {}
|
|
}
|