589a1f216f
Results with this revision: SHA256 rate 2.599MB/sec Debug 240MHz SW SHA256 rate 1.147MB/sec Release 80MHz SW SHA256 rate 3.469MB/sec Release 240MHz SW SHA256 rate 2.687MB/sec Release 240MHz SW + PSRAM workaround SHA256 rate 9.433MB/sec Debug 240MHz HW rev1 SHA256 rate 3.727MB/sec Release 80MHz HW rev1 SHA256 rate 10.961MB/sec Release 240MHz HW rev1 SHA256 rate 9.966MB/sec Release 240MHz HW rev1 + PRAM workaround SHA256 rate 10.974MB/sec Debug 240MHz HW rev3 SHA256 rate 4.362MB/sec Release 80MHz HW rev3 SHA256 rate 13.207MB/sec Release 240MHz HW rev3 Debug = Og, assertions enabled Release = O2, assertions disabled
36 lines
2.4 KiB
C
36 lines
2.4 KiB
C
#pragma once
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/* declare the performance here */
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#define IDF_PERFORMANCE_MAX_HTTPS_REQUEST_BIN_SIZE 800
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP 200
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM 300
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE 130
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#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL 1000
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 30
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 27
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 15
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#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 15
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/* Due to code size & linker layout differences interacting with cache, VFS
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microbenchmark currently runs slower with PSRAM enabled. */
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME 20000
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM 25000
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// throughput performance by iperf
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#define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT 45
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#define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT 40
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#define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT 64
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#define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT 50
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// events dispatched per second by event loop library
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH 25000
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM 21000
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// esp_sha() time to process 32KB of input data from RAM
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#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA1_32KB 5000
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#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA512_32KB 4500
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// AES-CBC hardware throughput (accounts for worst-case performance with PSRAM workaround)
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#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 8.2
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// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround)
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_DIV 70
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_SQRT 140
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// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
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#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 9.0
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