529 lines
17 KiB
C
529 lines
17 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <esp_types.h>
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#include <stdlib.h>
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#include <ctype.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "freertos/semphr.h"
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#include "freertos/timers.h"
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#include "esp_log.h"
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#include "esp_pm.h"
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#include "soc/rtc.h"
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#include "driver/rtc_io.h"
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#include "driver/dac.h"
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#include "sys/lock.h"
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#include "driver/gpio.h"
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#include "driver/adc.h"
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#include "adc1_private.h"
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#include "hal/adc_types.h"
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#include "hal/adc_hal.h"
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#define ADC_CHECK_RET(fun_ret) ({ \
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if (fun_ret != ESP_OK) { \
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ESP_LOGE(ADC_TAG,"%s:%d\n",__FUNCTION__,__LINE__); \
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return ESP_FAIL; \
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} \
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})
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static const char *ADC_TAG = "ADC";
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#define ADC_CHECK(a, str, ret_val) ({ \
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if (!(a)) { \
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ESP_LOGE(ADC_TAG,"%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str); \
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return (ret_val); \
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} \
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})
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#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
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#define ADC_CHANNEL_CHECK(periph, channel) ADC_CHECK(channel < SOC_ADC_CHANNEL_NUM(periph), "ADC"#periph" channel error", ESP_ERR_INVALID_ARG)
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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#define ADC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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#define ADC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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/*
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In ADC2, there're two locks used for different cases:
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1. lock shared with app and Wi-Fi:
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ESP32:
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When Wi-Fi using the ADC2, we assume it will never stop, so app checks the lock and returns immediately if failed.
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ESP32S2:
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The controller's control over the ADC is determined by the arbiter. There is no need to control by lock.
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2. lock shared between tasks:
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when several tasks sharing the ADC2, we want to guarantee
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all the requests will be handled.
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Since conversions are short (about 31us), app returns the lock very soon,
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we use a spinlock to stand there waiting to do conversions one by one.
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adc2_spinlock should be acquired first, then adc2_wifi_lock or rtc_spinlock.
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32
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//prevent ADC2 being used by wifi and other tasks at the same time.
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static _lock_t adc2_wifi_lock;
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/** For ESP32S2 the ADC2 The right to use ADC2 is controlled by the arbiter, and there is no need to set a lock. */
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#define ADC2_WIFI_LOCK_ACQUIRE() _lock_acquire( &adc2_wifi_lock )
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#define ADC2_WIFI_LOCK_RELEASE() _lock_release( &adc2_wifi_lock )
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#define ADC2_WIFI_LOCK_TRY_ACQUIRE() _lock_try_acquire( &adc2_wifi_lock )
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#define ADC2_WIFI_LOCK_CHECK() ((uint32_t *)adc2_wifi_lock != NULL)
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#elif defined CONFIG_IDF_TARGET_ESP32S2
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#define ADC2_WIFI_LOCK_ACQUIRE()
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#define ADC2_WIFI_LOCK_RELEASE()
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#define ADC2_WIFI_LOCK_TRY_ACQUIRE() (0) //WIFI controller and rtc controller have independent parameter configuration.
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#define ADC2_WIFI_LOCK_CHECK() (true)
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#endif
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//prevent ADC2 being used by tasks (regardless of WIFI)
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static portMUX_TYPE adc2_spinlock = portMUX_INITIALIZER_UNLOCKED;
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#define ADC2_ENTER_CRITICAL() portENTER_CRITICAL( &adc2_spinlock )
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#define ADC2_EXIT_CRITICAL() portEXIT_CRITICAL( &adc2_spinlock )
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//prevent ADC1 being used by I2S dma and other tasks at the same time.
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static _lock_t adc1_dma_lock;
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#define ADC1_DMA_LOCK_ACQUIRE() _lock_acquire( &adc1_dma_lock )
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#define ADC1_DMA_LOCK_RELEASE() _lock_release( &adc1_dma_lock )
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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#ifdef CONFIG_PM_ENABLE
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static esp_pm_lock_handle_t s_adc2_arbiter_lock;
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#endif //CONFIG_PM_ENABLE
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#endif //CONFIG_IDF_TARGET_ESP32S2
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/*---------------------------------------------------------------
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ADC Common
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---------------------------------------------------------------*/
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void adc_power_always_on(void)
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{
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ADC_ENTER_CRITICAL();
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adc_hal_set_power_manage(ADC_POWER_SW_ON);
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ADC_EXIT_CRITICAL();
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}
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void adc_power_on(void)
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{
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ADC_ENTER_CRITICAL();
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/* The power FSM controlled mode saves more power, while the ADC noise may get increased. */
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#ifndef CONFIG_ADC_FORCE_XPD_FSM
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/* Set the power always on to increase precision. */
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adc_hal_set_power_manage(ADC_POWER_SW_ON);
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#else
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/* Use the FSM to turn off the power while not used to save power. */
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if (adc_hal_get_power_manage() != ADC_POWER_BY_FSM) {
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adc_hal_set_power_manage(ADC_POWER_SW_ON);
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}
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#endif
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ADC_EXIT_CRITICAL();
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}
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void adc_power_off(void)
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{
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ADC_ENTER_CRITICAL();
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adc_hal_set_power_manage(ADC_POWER_SW_OFF);
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ADC_EXIT_CRITICAL();
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}
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esp_err_t adc_set_clk_div(uint8_t clk_div)
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{
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ADC_ENTER_CRITICAL();
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adc_hal_digi_set_clk_div(clk_div);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
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{
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gpio_num_t gpio_num = 0;
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if (adc_unit & ADC_UNIT_1) {
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ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
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gpio_num = ADC_GET_IO_NUM(ADC_NUM_1, channel);
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}
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if (adc_unit & ADC_UNIT_2) {
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ADC_CHANNEL_CHECK(ADC_NUM_2, channel);
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gpio_num = ADC_GET_IO_NUM(ADC_NUM_2, channel);
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}
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ADC_CHECK_RET(rtc_gpio_init(gpio_num));
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ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
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ADC_CHECK_RET(gpio_set_pull_mode(gpio_num, GPIO_FLOATING));
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return ESP_OK;
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}
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esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
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{
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ADC_ENTER_CRITICAL();
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if (adc_unit & ADC_UNIT_1) {
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adc_hal_rtc_output_invert(ADC_NUM_1, inv_en);
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}
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if (adc_unit & ADC_UNIT_2) {
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adc_hal_rtc_output_invert(ADC_NUM_1, inv_en);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
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{
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#ifdef CONFIG_IDF_TARGET_ESP32
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ADC_CHECK(bits < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
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#elif defined CONFIG_IDF_TARGET_ESP32S2
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ADC_CHECK(bits == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG);
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#endif
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ADC_ENTER_CRITICAL();
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if (adc_unit & ADC_UNIT_1) {
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adc_hal_rtc_set_output_format(ADC_NUM_1, bits);
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}
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if (adc_unit & ADC_UNIT_2) {
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adc_hal_rtc_set_output_format(ADC_NUM_2, bits);
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adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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/**
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* @brief Reset RTC controller FSM.
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*
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* @return
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* - ESP_OK Success
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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esp_err_t adc_rtc_reset(void)
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{
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ADC_ENTER_CRITICAL();
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adc_hal_rtc_reset();
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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static inline void adc_set_init_code(adc_ll_num_t adc_n, adc_channel_t channel)
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{
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adc_atten_t atten = adc_hal_get_atten(adc_n, channel);
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uint32_t cal_val = adc_hal_calibration(adc_n, channel, atten, true, false);
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adc_hal_set_calibration_param(adc_n, cal_val);
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ESP_LOGD(ADC_TAG, "Set cal adc %d\n", cal_val);
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}
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#endif
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/*-------------------------------------------------------------------------------------
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* ADC1
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*------------------------------------------------------------------------------------*/
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esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
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{
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ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
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int io = ADC_GET_IO_NUM(ADC_NUM_1, channel);
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if (io < 0) {
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return ESP_ERR_INVALID_ARG;
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} else {
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*gpio_num = (gpio_num_t)io;
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}
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return ESP_OK;
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}
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esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
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{
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ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
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ADC_CHECK(atten < ADC_ATTEN_MAX, "ADC Atten Err", ESP_ERR_INVALID_ARG);
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adc_gpio_init(ADC_UNIT_1, channel);
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ADC_ENTER_CRITICAL();
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adc_hal_set_atten(ADC_NUM_1, channel, atten);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc1_config_width(adc_bits_width_t width_bit)
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{
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#ifdef CONFIG_IDF_TARGET_ESP32
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ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
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#elif defined CONFIG_IDF_TARGET_ESP32S2
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ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG);
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#endif
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ADC_ENTER_CRITICAL();
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adc_hal_rtc_set_output_format(ADC_NUM_1, width_bit);
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adc_hal_rtc_output_invert(ADC_NUM_1, SOC_ADC1_DATA_INVERT_DEFAULT);
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adc_hal_set_sar_clk_div(ADC_NUM_1, SOC_ADC_SAR_CLK_DIV_DEFAULT(ADC_NUM_1));
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc1_dma_mode_acquire(void)
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{
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/* Use locks to avoid digtal and RTC controller conflicts.
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for adc1, block until acquire the lock. */
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ADC1_DMA_LOCK_ACQUIRE();
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ESP_LOGD( ADC_TAG, "dma mode takes adc1 lock." );
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ADC_ENTER_CRITICAL();
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adc_hal_set_power_manage(ADC_POWER_SW_ON);
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/* switch SARADC into DIG channel */
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_DIG);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc1_rtc_mode_acquire(void)
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{
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/* Use locks to avoid digtal and RTC controller conflicts.
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for adc1, block until acquire the lock. */
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ADC1_DMA_LOCK_ACQUIRE();
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ADC_ENTER_CRITICAL();
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/* switch SARADC into RTC channel. */
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_RTC);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc1_lock_release(void)
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{
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ADC_CHECK((uint32_t *)adc1_dma_lock != NULL, "adc1 lock release called before acquire", ESP_ERR_INVALID_STATE );
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/* Use locks to avoid digtal and RTC controller conflicts. for adc1, block until acquire the lock. */
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ADC1_DMA_LOCK_RELEASE();
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return ESP_OK;
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}
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int adc1_get_raw(adc1_channel_t channel)
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{
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int adc_value;
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ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
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adc1_rtc_mode_acquire();
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adc_power_on();
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ADC_ENTER_CRITICAL();
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#ifdef CONFIG_IDF_TARGET_ESP32
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adc_hal_hall_disable(); //Disable other peripherals.
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adc_hal_amp_disable(); //Currently the LNA is not open, close it by default.
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#endif
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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adc_set_init_code(ADC_NUM_1, channel); // calibration for adc
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#endif
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_RTC); //Set controller
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adc_hal_convert(ADC_NUM_1, channel, &adc_value); //Start conversion, For ADC1, the data always valid.
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ADC_EXIT_CRITICAL();
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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adc_hal_rtc_reset(); //Reset FSM of rtc controller
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#endif
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adc1_lock_release();
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return adc_value;
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}
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int adc1_get_voltage(adc1_channel_t channel) //Deprecated. Use adc1_get_raw() instead
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{
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return adc1_get_raw(channel);
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}
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void adc1_ulp_enable(void)
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{
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adc_power_on();
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ADC_ENTER_CRITICAL();
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_ULP);
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/* since most users do not need LNA and HALL with uLP, we disable them here
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open them in the uLP if needed. */
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#ifdef CONFIG_IDF_TARGET_ESP32
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/* disable other peripherals. */
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adc_hal_hall_disable();
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adc_hal_amp_disable();
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#endif
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ADC_EXIT_CRITICAL();
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}
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/*---------------------------------------------------------------
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ADC2
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---------------------------------------------------------------*/
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esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num)
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{
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ADC_CHANNEL_CHECK(ADC_NUM_2, channel);
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int io = ADC_GET_IO_NUM(ADC_NUM_2, channel);
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if (io < 0) {
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return ESP_ERR_INVALID_ARG;
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} else {
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*gpio_num = (gpio_num_t)io;
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}
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return ESP_OK;
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}
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/** For ESP32S2 the ADC2 The right to use ADC2 is controlled by the arbiter, and there is no need to set a lock.*/
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esp_err_t adc2_wifi_acquire(void)
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{
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/* Wi-Fi module will use adc2. Use locks to avoid conflicts. */
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ADC2_WIFI_LOCK_ACQUIRE();
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ESP_LOGD( ADC_TAG, "Wi-Fi takes adc2 lock." );
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return ESP_OK;
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}
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esp_err_t adc2_wifi_release(void)
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{
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ADC_CHECK(ADC2_WIFI_LOCK_CHECK(), "wifi release called before acquire", ESP_ERR_INVALID_STATE );
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ADC2_WIFI_LOCK_RELEASE();
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ESP_LOGD( ADC_TAG, "Wi-Fi returns adc2 lock." );
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return ESP_OK;
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}
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static esp_err_t adc2_pad_init(adc2_channel_t channel)
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{
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gpio_num_t gpio_num = 0;
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ADC_CHECK_RET(adc2_pad_get_io_num(channel, &gpio_num));
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ADC_CHECK_RET(rtc_gpio_init(gpio_num));
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ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
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ADC_CHECK_RET(gpio_set_pull_mode(gpio_num, GPIO_FLOATING));
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return ESP_OK;
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}
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esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
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{
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ADC_CHANNEL_CHECK(ADC_NUM_2, channel);
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ADC_CHECK(atten <= ADC_ATTEN_11db, "ADC2 Atten Err", ESP_ERR_INVALID_ARG);
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adc2_pad_init(channel);
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ADC2_ENTER_CRITICAL();
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//avoid collision with other tasks
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if ( ADC2_WIFI_LOCK_TRY_ACQUIRE() == -1 ) {
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//try the lock, return if failed (wifi using).
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ADC2_EXIT_CRITICAL();
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return ESP_ERR_TIMEOUT;
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}
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adc_hal_set_atten(ADC_NUM_2, channel, atten);
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ADC2_WIFI_LOCK_RELEASE();
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ADC2_EXIT_CRITICAL();
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return ESP_OK;
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}
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static inline void adc2_config_width(adc_bits_width_t width_bit)
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{
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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#ifdef CONFIG_PM_ENABLE
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/* Lock APB clock. */
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if (s_adc2_arbiter_lock == NULL) {
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esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc2", &s_adc2_arbiter_lock);
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}
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#endif //CONFIG_PM_ENABLE
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#endif //CONFIG_IDF_TARGET_ESP32S2
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ADC_ENTER_CRITICAL();
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adc_hal_rtc_set_output_format(ADC_NUM_2, width_bit);
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adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT);
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adc_hal_rtc_output_invert(ADC_NUM_2, SOC_ADC2_DATA_INVERT_DEFAULT);
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adc_hal_set_sar_clk_div(ADC_NUM_2, SOC_ADC_SAR_CLK_DIV_DEFAULT(ADC_NUM_2));
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ADC_EXIT_CRITICAL();
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}
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static inline void adc2_dac_disable( adc2_channel_t channel)
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{
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#ifdef CONFIG_IDF_TARGET_ESP32
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if ( channel == ADC2_CHANNEL_8 ) { // the same as DAC channel 1
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dac_output_disable(DAC_CHANNEL_1);
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} else if ( channel == ADC2_CHANNEL_9 ) {
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|
dac_output_disable(DAC_CHANNEL_2);
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|
}
|
|
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
|
if ( channel == ADC2_CHANNEL_6 ) { // the same as DAC channel 1
|
|
dac_output_disable(DAC_CHANNEL_1);
|
|
} else if ( channel == ADC2_CHANNEL_7 ) {
|
|
dac_output_disable(DAC_CHANNEL_2);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* @note For ESP32S2:
|
|
* The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
|
|
* Or, the RTC controller will fail when get raw data.
|
|
* This issue does not occur on digital controllers (DMA mode), and the hardware guarantees that there will be no errors.
|
|
*/
|
|
esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out)
|
|
{
|
|
int adc_value = 0;
|
|
|
|
ADC_CHECK(raw_out != NULL, "ADC out value err", ESP_ERR_INVALID_ARG);
|
|
ADC_CHECK(channel < ADC2_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
|
ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
|
|
#elif defined CONFIG_IDF_TARGET_ESP32S2
|
|
ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG);
|
|
#endif
|
|
|
|
adc_power_on(); //in critical section with whole rtc module
|
|
|
|
ADC2_ENTER_CRITICAL(); //avoid collision with other tasks
|
|
|
|
if ( ADC2_WIFI_LOCK_TRY_ACQUIRE() == -1 ) { //try the lock, return if failed (wifi using).
|
|
ADC2_EXIT_CRITICAL();
|
|
return ESP_ERR_TIMEOUT;
|
|
}
|
|
#ifdef CONFIG_ADC_DISABLE_DAC
|
|
adc2_dac_disable(channel); //disable other peripherals
|
|
#endif
|
|
adc2_config_width(width_bit); // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
|
|
#ifdef CONFIG_IDF_TARGET_ESP32S2
|
|
adc_set_init_code(ADC_NUM_2, channel); // calibration for adc
|
|
#endif
|
|
adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC);// set controller
|
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32S2
|
|
#ifdef CONFIG_PM_ENABLE
|
|
if (s_adc2_arbiter_lock) {
|
|
esp_pm_lock_acquire(s_adc2_arbiter_lock);
|
|
}
|
|
#endif //CONFIG_PM_ENABLE
|
|
#endif //CONFIG_IDF_TARGET_ESP32
|
|
|
|
if (adc_hal_convert(ADC_NUM_2, channel, &adc_value)) {
|
|
adc_value = -1;
|
|
}
|
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32S2
|
|
#ifdef CONFIG_PM_ENABLE
|
|
/* Release APB clock. */
|
|
if (s_adc2_arbiter_lock) {
|
|
esp_pm_lock_release(s_adc2_arbiter_lock);
|
|
}
|
|
#endif //CONFIG_PM_ENABLE
|
|
#endif //CONFIG_IDF_TARGET_ESP32
|
|
|
|
ADC2_WIFI_LOCK_RELEASE();
|
|
ADC2_EXIT_CRITICAL();
|
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32S2
|
|
adc_rtc_reset();
|
|
#endif
|
|
|
|
if (adc_value < 0) {
|
|
ESP_LOGD( ADC_TAG, "ADC2 ARB: Return data is invalid." );
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
*raw_out = adc_value;
|
|
return ESP_OK;
|
|
}
|
|
|