fe767855df
1. Use BIT[7:5] of EID to determine psram size 2. Add ID support for 16Mbit psram 3. Remove module reset on SPI1 4. Confirmed with the vendor that only the old 32Mbit psram need special clock timing. For other psram chips, we should use standard QPI mode.
297 lines
11 KiB
C
297 lines
11 KiB
C
/*
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Abstraction layer for spi-ram. For now, it's no more than a stub for the spiram_psram functions, but if
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we add more types of external RAM memory, this can be made into a more intelligent dispatcher.
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*/
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// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <string.h>
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_spiram.h"
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#include "spiram_psram.h"
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "soc/soc.h"
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#include "esp_heap_caps_init.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/dport_reg.h"
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#include "rom/cache.h"
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#include "esp_himem.h"
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#if CONFIG_FREERTOS_UNICORE
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#else
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#if CONFIG_MEMMAP_SPIRAM_CACHE_EVENODD
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#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
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#else
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#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
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#endif
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#endif
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#if CONFIG_SPIRAM_SUPPORT
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static const char* TAG = "spiram";
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#if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
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#define PSRAM_SPEED PSRAM_CACHE_F40M_S40M
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#elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define PSRAM_SPEED PSRAM_CACHE_F80M_S40M
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#elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define PSRAM_SPEED PSRAM_CACHE_F80M_S80M
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#else
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#error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
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#endif
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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extern uint8_t _ext_ram_bss_start, _ext_ram_bss_end;
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#endif
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static bool spiram_inited=false;
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//If no function in esp_himem.c is used, this function will be linked into the
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//binary instead of the one in esp_himem.c, automatically making sure no memory
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//is reserved if no himem function is used.
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size_t __attribute__((weak)) esp_himem_reserved_area_size() {
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return 0;
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}
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static int spiram_size_usable_for_malloc()
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{
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int s=esp_spiram_get_size();
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if (s>4*1024*1024) s=4*1024*1024; //we can map at most 4MiB
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return s-esp_himem_reserved_area_size();
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}
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/*
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Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
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true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
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initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
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*/
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bool esp_spiram_test()
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{
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volatile int *spiram=(volatile int*)SOC_EXTRAM_DATA_LOW;
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size_t p;
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size_t s=spiram_size_usable_for_malloc();
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int errct=0;
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int initial_err=-1;
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for (p=0; p<(s/sizeof(int)); p+=8) {
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spiram[p]=p^0xAAAAAAAA;
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}
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for (p=0; p<(s/sizeof(int)); p+=8) {
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if (spiram[p]!=(p^0xAAAAAAAA)) {
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errct++;
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if (errct==1) initial_err=p*4;
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}
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}
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if (errct) {
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ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, s/32, initial_err+SOC_EXTRAM_DATA_LOW);
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return false;
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} else {
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ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");
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return true;
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}
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}
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void IRAM_ATTR esp_spiram_init_cache()
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{
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//Enable external RAM in MMU
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cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
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//Flush and enable icache for APP CPU
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#if !CONFIG_FREERTOS_UNICORE
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
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cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
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#endif
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}
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esp_spiram_size_t esp_spiram_get_chip_size()
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{
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if (!spiram_inited) {
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ESP_EARLY_LOGE(TAG, "SPI RAM not initialized");
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return ESP_SPIRAM_SIZE_INVALID;
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}
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psram_size_t psram_size = psram_get_size();
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switch (psram_size) {
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case PSRAM_SIZE_16MBITS:
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return ESP_SPIRAM_SIZE_16MBITS;
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case PSRAM_SIZE_32MBITS:
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return ESP_SPIRAM_SIZE_32MBITS;
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case PSRAM_SIZE_64MBITS:
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return ESP_SPIRAM_SIZE_64MBITS;
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default:
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return ESP_SPIRAM_SIZE_INVALID;
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}
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}
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esp_err_t esp_spiram_init()
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{
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esp_err_t r;
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r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
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if (r != ESP_OK) {
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#if CONFIG_SPIRAM_IGNORE_NOTFOUND
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ESP_EARLY_LOGE(TAG, "SPI RAM enabled but initialization failed. Bailing out.");
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#endif
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return r;
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}
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spiram_inited=true; //note: this needs to be set before esp_spiram_get_chip_*/esp_spiram_get_size calls
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#if (CONFIG_SPIRAM_SIZE != -1)
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if (esp_spiram_get_size()!=CONFIG_SPIRAM_SIZE) {
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ESP_EARLY_LOGE(TAG, "Expected %dKiB chip but found %dKiB chip. Bailing out..", CONFIG_SPIRAM_SIZE/1024, esp_spiram_get_size()/1024);
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return ESP_ERR_INVALID_SIZE;
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}
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#endif
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ESP_EARLY_LOGI(TAG, "Found %dMBit SPI RAM device",
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(esp_spiram_get_size()*8)/(1024*1024));
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ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_F40M_S40M ? "flash 40m sram 40m" : \
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PSRAM_SPEED == PSRAM_CACHE_F80M_S40M ? "flash 80m sram 40m" : \
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PSRAM_SPEED == PSRAM_CACHE_F80M_S80M ? "flash 80m sram 80m" : "ERROR");
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ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \
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(PSRAM_MODE==PSRAM_VADDR_MODE_EVENODD)?"even/odd (2-core)": \
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(PSRAM_MODE==PSRAM_VADDR_MODE_LOWHIGH)?"low/high (2-core)": \
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(PSRAM_MODE==PSRAM_VADDR_MODE_NORMAL)?"normal (1-core)":"ERROR");
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return ESP_OK;
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}
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esp_err_t esp_spiram_add_to_heapalloc()
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{
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//Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's
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//no need to explicitly specify them.
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#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (spiram_size_usable_for_malloc() - (&_ext_ram_bss_end - &_ext_ram_bss_start))/1024);
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return heap_caps_add_region((intptr_t)&_ext_ram_bss_end, (intptr_t)SOC_EXTRAM_DATA_LOW + spiram_size_usable_for_malloc()-1);
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#else
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ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", spiram_size_usable_for_malloc()/1024);
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return heap_caps_add_region((intptr_t)SOC_EXTRAM_DATA_LOW, (intptr_t)SOC_EXTRAM_DATA_LOW + spiram_size_usable_for_malloc()-1);
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#endif
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}
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static uint8_t *dma_heap;
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esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
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ESP_EARLY_LOGI(TAG, "Reserving pool of %dK of internal memory for DMA/internal allocations", size/1024);
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/* Pool may be allocated in multiple non-contiguous chunks, depending on available RAM */
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while (size > 0) {
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size_t next_size = heap_caps_get_largest_free_block(MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
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next_size = MIN(next_size, size);
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ESP_EARLY_LOGD(TAG, "Allocating block of size %d bytes", next_size);
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dma_heap = heap_caps_malloc(next_size, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL);
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if (!dma_heap || next_size == 0) {
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return ESP_ERR_NO_MEM;
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}
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uint32_t caps[] = { 0, MALLOC_CAP_DMA|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT };
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esp_err_t e = heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, (intptr_t) dma_heap+next_size-1);
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if (e != ESP_OK) {
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return e;
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}
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size -= next_size;
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}
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return ESP_OK;
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}
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size_t esp_spiram_get_size()
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{
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psram_size_t size=esp_spiram_get_chip_size();
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if (size==PSRAM_SIZE_16MBITS) return 2*1024*1024;
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if (size==PSRAM_SIZE_32MBITS) return 4*1024*1024;
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if (size==PSRAM_SIZE_64MBITS) return 8*1024*1024;
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return CONFIG_SPIRAM_SIZE;
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}
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/*
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Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
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otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
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Note that this routine assumes some unique mapping for the first 2 banks of the PSRAM memory range, as well as the
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2 banks after the 2 MiB mark.
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*/
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void IRAM_ATTR esp_spiram_writeback_cache()
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{
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int x;
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volatile int i=0;
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volatile uint8_t *psram=(volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
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int cache_was_disabled=0;
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if (!spiram_inited) return;
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//We need cache enabled for this to work. Re-enable it if needed; make sure we
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//disable it again on exit as well.
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if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) {
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cache_was_disabled|=(1<<0);
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) {
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cache_was_disabled|=(1<<1);
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
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}
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#endif
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#if (PSRAM_MODE != PSRAM_VADDR_MODE_LOWHIGH)
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/*
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Single-core and even/odd mode only have 32K of cache evenly distributed over the address lines. We can clear
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the cache by just reading 64K worth of cache lines.
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*/.
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for (x=0; x<1024*64; x+=32) {
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i+=psram[x];
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}
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#else
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/*
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Low/high psram cache mode uses one 32KB cache for the lowest 2MiB of SPI flash and another 32K for the highest
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2MiB. Clear this by reading from both regions.
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Note: this assumes the amount of external RAM is >2MB. If it is 2MB or less, what this code does is undefined. If
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we ever support external RAM chips of 2MB or smaller, this may need adjusting.
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*/
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for (x=0; x<1024*64; x+=32) {
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i+=psram[x];
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i+=psram[x+(1024*1024*2)];
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}
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#endif
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if (cache_was_disabled&(1<<0)) {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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if (cache_was_disabled&(1<<1)) {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
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}
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#endif
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}
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/**
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* @brief If SPI RAM(PSRAM) has been initialized
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*
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* @return true SPI RAM has been initialized successfully
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* @return false SPI RAM hasn't been initialized or initialized failed
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*/
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bool esp_spiram_is_initialized()
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{
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return spiram_inited;
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}
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#endif
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