706 lines
30 KiB
C
706 lines
30 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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Architecture:
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We can initialize a SPI driver, but we don't talk to the SPI driver itself, we address a device. A device essentially
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is a combination of SPI port and CS pin, plus some information about the specifics of communication to the device
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(timing, command/address length etc)
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The essence of the interface to a device is a set of queues; one per device. The idea is that to send something to a SPI
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device, you allocate a transaction descriptor. It contains some information about the transfer like the lenghth, address,
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command etc, plus pointers to transmit and receive buffer. The address of this block gets pushed into the transmit queue.
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The SPI driver does its magic, and sends and retrieves the data eventually. The data gets written to the receive buffers,
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if needed the transaction descriptor is modified to indicate returned parameters and the entire thing goes into the return
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queue, where whatever software initiated the transaction can retrieve it.
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The entire thing is run from the SPI interrupt handler. If SPI is done transmitting/receiving but nothing is in the queue,
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it will not clear the SPI interrupt but just disable it. This way, when a new thing is sent, pushing the packet into the send
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queue and re-enabling the interrupt will trigger the interrupt again, which can then take care of the sending.
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*/
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#include <string.h>
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#include "driver/spi_master.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/spi_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_struct.h"
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#include "soc/rtc_cntl_reg.h"
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#include "rom/ets_sys.h"
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_intr.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/xtensa_api.h"
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#include "freertos/task.h"
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#include "freertos/ringbuf.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "soc/uart_struct.h"
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#include "rom/lldesc.h"
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#include "driver/uart.h"
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#include "driver/gpio.h"
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#include "driver/periph_ctrl.h"
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#include "esp_heap_alloc_caps.h"
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typedef struct spi_device_t spi_device_t;
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#define NO_CS 3 //Number of CS pins per SPI host
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typedef struct {
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spi_device_t *device[NO_CS];
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intr_handle_t intr;
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spi_dev_t *hw;
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spi_transaction_t *cur_trans;
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int cur_cs;
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lldesc_t dmadesc_tx, dmadesc_rx;
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bool no_gpio_matrix;
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} spi_host_t;
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struct spi_device_t {
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QueueHandle_t trans_queue;
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QueueHandle_t ret_queue;
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spi_device_interface_config_t cfg;
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spi_host_t *host;
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};
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static spi_host_t *spihost[3];
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static const char *SPI_TAG = "spi_master";
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#define SPI_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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}
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/*
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Stores a bunch of per-spi-peripheral data.
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*/
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typedef struct {
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const uint8_t spiclk_out; //GPIO mux output signals
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const uint8_t spid_out;
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const uint8_t spiq_out;
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const uint8_t spiwp_out;
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const uint8_t spihd_out;
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const uint8_t spid_in; //GPIO mux input signals
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const uint8_t spiq_in;
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const uint8_t spiwp_in;
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const uint8_t spihd_in;
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const uint8_t spics_out[3]; // /CS GPIO output mux signals
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const uint8_t spiclk_native; //IO pins of IO_MUX muxed signals
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const uint8_t spid_native;
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const uint8_t spiq_native;
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const uint8_t spiwp_native;
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const uint8_t spihd_native;
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const uint8_t spics0_native;
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const uint8_t irq; //irq source for interrupt mux
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const uint8_t irq_dma; //dma irq source for interrupt mux
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const periph_module_t module; //peripheral module, for enabling clock etc
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spi_dev_t *hw; //Pointer to the hardware registers
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} spi_signal_conn_t;
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/*
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Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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static const spi_signal_conn_t io_signal[3]={
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{
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.spiclk_out=SPICLK_OUT_IDX,
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.spid_out=SPID_OUT_IDX,
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.spiq_out=SPIQ_OUT_IDX,
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.spiwp_out=SPIWP_OUT_IDX,
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.spihd_out=SPIHD_OUT_IDX,
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.spid_in=SPID_IN_IDX,
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.spiq_in=SPIQ_IN_IDX,
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.spiwp_in=SPIWP_IN_IDX,
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.spihd_in=SPIHD_IN_IDX,
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.spics_out={SPICS0_OUT_IDX, SPICS1_OUT_IDX, SPICS2_OUT_IDX},
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.spiclk_native=6,
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.spid_native=8,
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.spiq_native=7,
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.spiwp_native=10,
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.spihd_native=9,
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.spics0_native=11,
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.irq=ETS_SPI1_INTR_SOURCE,
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.irq_dma=ETS_SPI1_DMA_INTR_SOURCE,
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.module=PERIPH_SPI_MODULE,
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.hw=&SPI1
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}, {
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.spiclk_out=HSPICLK_OUT_IDX,
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.spid_out=HSPID_OUT_IDX,
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.spiq_out=HSPIQ_OUT_IDX,
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.spiwp_out=HSPIWP_OUT_IDX,
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.spihd_out=HSPIHD_OUT_IDX,
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.spid_in=HSPID_IN_IDX,
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.spiq_in=HSPIQ_IN_IDX,
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.spiwp_in=HSPIWP_IN_IDX,
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.spihd_in=HSPIHD_IN_IDX,
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.spics_out={HSPICS0_OUT_IDX, HSPICS1_OUT_IDX, HSPICS2_OUT_IDX},
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.spiclk_native=14,
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.spid_native=13,
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.spiq_native=12,
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.spiwp_native=2,
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.spihd_native=4,
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.spics0_native=15,
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.irq=ETS_SPI2_INTR_SOURCE,
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.irq_dma=ETS_SPI2_DMA_INTR_SOURCE,
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.module=PERIPH_HSPI_MODULE,
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.hw=&SPI2
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}, {
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.spiclk_out=VSPICLK_OUT_IDX,
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.spid_out=VSPID_OUT_IDX,
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.spiq_out=VSPIQ_OUT_IDX,
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.spiwp_out=VSPIWP_OUT_IDX,
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.spihd_out=VSPIHD_OUT_IDX,
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.spid_in=VSPID_IN_IDX,
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.spiq_in=VSPIQ_IN_IDX,
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.spiwp_in=VSPIWP_IN_IDX,
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.spihd_in=VSPIHD_IN_IDX,
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.spics_out={VSPICS0_OUT_IDX, VSPICS1_OUT_IDX, VSPICS2_OUT_IDX},
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.spiclk_native=18,
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.spid_native=23,
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.spiq_native=19,
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.spiwp_native=22,
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.spihd_native=21,
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.spics0_native=5,
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.irq=ETS_SPI3_INTR_SOURCE,
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.irq_dma=ETS_SPI3_DMA_INTR_SOURCE,
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.module=PERIPH_VSPI_MODULE,
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.hw=&SPI3
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}
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};
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static void spi_intr(void *arg);
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esp_err_t spi_bus_initialize(spi_host_device_t host, spi_bus_config_t *bus_config, int dma_chan)
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{
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bool native=true;
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/* ToDo: remove this when we have flash operations cooperating with this */
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SPI_CHECK(host!=SPI_HOST, "SPI1 is not supported", ESP_ERR_NOT_SUPPORTED);
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SPI_CHECK(host>=SPI_HOST && host<=VSPI_HOST, "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]==NULL, "host already in use", ESP_ERR_INVALID_STATE);
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SPI_CHECK(bus_config->mosi_io_num<0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num), "spid pin invalid", ESP_ERR_INVALID_ARG);
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SPI_CHECK(bus_config->sclk_io_num<0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->sclk_io_num), "spiclk pin invalid", ESP_ERR_INVALID_ARG);
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SPI_CHECK(bus_config->miso_io_num<0 || GPIO_IS_VALID_GPIO(bus_config->miso_io_num), "spiq pin invalid", ESP_ERR_INVALID_ARG);
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SPI_CHECK(bus_config->quadwp_io_num<0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadwp_io_num), "spiwp pin invalid", ESP_ERR_INVALID_ARG);
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SPI_CHECK(bus_config->quadhd_io_num<0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadhd_io_num), "spihd pin invalid", ESP_ERR_INVALID_ARG);
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//The host struct contains two dma descriptors, so we need DMA'able memory for this.
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spihost[host]=pvPortMallocCaps(sizeof(spi_host_t), MALLOC_CAP_DMA);
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if (spihost[host]==NULL) return ESP_ERR_NO_MEM;
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memset(spihost[host], 0, sizeof(spi_host_t));
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//Check if the selected pins correspond to the native pins of the peripheral
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if (bus_config->mosi_io_num >= 0 && bus_config->mosi_io_num!=io_signal[host].spid_native) native=false;
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if (bus_config->miso_io_num >= 0 && bus_config->miso_io_num!=io_signal[host].spiq_native) native=false;
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if (bus_config->sclk_io_num >= 0 && bus_config->sclk_io_num!=io_signal[host].spiclk_native) native=false;
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if (bus_config->quadwp_io_num >= 0 && bus_config->quadwp_io_num!=io_signal[host].spiwp_native) native=false;
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if (bus_config->quadhd_io_num >= 0 && bus_config->quadhd_io_num!=io_signal[host].spihd_native) native=false;
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spihost[host]->no_gpio_matrix=native;
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if (native) {
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//All SPI native pin selections resolve to 1, so we put that here instead of trying to figure
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//out which FUNC_GPIOx_xSPIxx to grab; they all are defined to 1 anyway.
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if (bus_config->mosi_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], 1);
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if (bus_config->miso_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], 1);
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if (bus_config->quadwp_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], 1);
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if (bus_config->quadhd_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], 1);
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if (bus_config->sclk_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], 1);
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} else {
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//Use GPIO
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if (bus_config->mosi_io_num>0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_OUTPUT);
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gpio_matrix_out(bus_config->mosi_io_num, io_signal[host].spid_out, false, false);
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gpio_matrix_in(bus_config->mosi_io_num, io_signal[host].spid_in, false);
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}
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if (bus_config->miso_io_num>0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT);
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gpio_matrix_out(bus_config->miso_io_num, io_signal[host].spiq_out, false, false);
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gpio_matrix_in(bus_config->miso_io_num, io_signal[host].spiq_in, false);
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}
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if (bus_config->quadwp_io_num>0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_OUTPUT);
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gpio_matrix_out(bus_config->quadwp_io_num, io_signal[host].spiwp_out, false, false);
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gpio_matrix_in(bus_config->quadwp_io_num, io_signal[host].spiwp_in, false);
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}
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if (bus_config->quadhd_io_num>0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_OUTPUT);
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gpio_matrix_out(bus_config->quadhd_io_num, io_signal[host].spihd_out, false, false);
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gpio_matrix_in(bus_config->quadhd_io_num, io_signal[host].spihd_in, false);
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}
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if (bus_config->sclk_io_num>0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_OUTPUT);
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gpio_matrix_out(bus_config->sclk_io_num, io_signal[host].spiclk_out, false, false);
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}
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}
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periph_module_enable(io_signal[host].module);
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esp_intr_alloc(io_signal[host].irq, ESP_INTR_FLAG_INTRDISABLED, spi_intr, (void*)spihost[host], &spihost[host]->intr);
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spihost[host]->hw=io_signal[host].hw;
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//Reset DMA
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spihost[host]->hw->dma_conf.val|=SPI_OUT_RST|SPI_AHBM_RST|SPI_AHBM_FIFO_RST;
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spihost[host]->hw->dma_out_link.start=0;
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spihost[host]->hw->dma_in_link.start=0;
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spihost[host]->hw->dma_conf.val&=~(SPI_OUT_RST|SPI_AHBM_RST|SPI_AHBM_FIFO_RST);
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//Disable unneeded ints
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spihost[host]->hw->slave.rd_buf_done=0;
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spihost[host]->hw->slave.wr_buf_done=0;
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spihost[host]->hw->slave.rd_sta_done=0;
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spihost[host]->hw->slave.wr_sta_done=0;
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spihost[host]->hw->slave.rd_buf_inten=0;
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spihost[host]->hw->slave.wr_buf_inten=0;
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spihost[host]->hw->slave.rd_sta_inten=0;
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spihost[host]->hw->slave.wr_sta_inten=0;
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//Force a transaction done interrupt. This interrupt won't fire yet because we initialized the SPI interrupt as
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//disabled. This way, we can just enable the SPI interrupt and the interrupt handler will kick in, handling
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//any transactions that are queued.
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spihost[host]->hw->slave.trans_inten=1;
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spihost[host]->hw->slave.trans_done=1;
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//Select DMA channel.
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SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2));
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return ESP_OK;
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}
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esp_err_t spi_bus_free(spi_host_device_t host)
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{
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int x;
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SPI_CHECK(host>=SPI_HOST && host<=VSPI_HOST, "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]!=NULL, "host not in use", ESP_ERR_INVALID_STATE);
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for (x=0; x<NO_CS; x++) {
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SPI_CHECK(spihost[host]->device[x]==NULL, "not all CSses freed", ESP_ERR_INVALID_STATE);
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}
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spihost[host]->hw->slave.trans_inten=0;
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spihost[host]->hw->slave.trans_done=0;
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esp_intr_free(spihost[host]->intr);
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periph_module_disable(io_signal[host].module);
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free(spihost[host]);
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spihost[host]=NULL;
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return ESP_OK;
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}
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/*
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Add a device. This allocates a CS line for the device, allocates memory for the device structure and hooks
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up the CS pin to whatever is specified.
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*/
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esp_err_t spi_bus_add_device(spi_host_device_t host, spi_device_interface_config_t *dev_config, spi_device_handle_t *handle)
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{
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int freecs;
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SPI_CHECK(host>=SPI_HOST && host<=VSPI_HOST, "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]!=NULL, "host not initialized", ESP_ERR_INVALID_STATE);
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SPI_CHECK(dev_config->spics_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(dev_config->spics_io_num), "spics pin invalid", ESP_ERR_INVALID_ARG);
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SPI_CHECK(dev_config->clock_speed_hz > 0, "invalid sclk speed", ESP_ERR_INVALID_ARG);
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for (freecs=0; freecs<NO_CS; freecs++) {
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//See if this slot is free; reserve if it is by putting a dummy pointer in the slot. We use an atomic compare&swap to make this thread-safe.
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if (__sync_bool_compare_and_swap(&spihost[host]->device[freecs], NULL, (spi_device_t *)1)) break;
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}
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SPI_CHECK(freecs!=NO_CS, "no free cs pins for host", ESP_ERR_NOT_FOUND);
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//The hardware looks like it would support this, but actually setting cs_ena_pretrans when transferring in full
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//duplex mode does absolutely nothing on the ESP32.
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SPI_CHECK(dev_config->cs_ena_pretrans==0 || (dev_config->flags & SPI_DEVICE_HALFDUPLEX), "cs pretrans delay incompatible with full-duplex", ESP_ERR_INVALID_ARG);
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//Allocate memory for device
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spi_device_t *dev=malloc(sizeof(spi_device_t));
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if (dev==NULL) return ESP_ERR_NO_MEM;
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memset(dev, 0, sizeof(spi_device_t));
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spihost[host]->device[freecs]=dev;
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//Allocate queues, set defaults
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dev->trans_queue=xQueueCreate(dev_config->queue_size, sizeof(spi_transaction_t *));
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dev->ret_queue=xQueueCreate(dev_config->queue_size, sizeof(spi_transaction_t *));
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if (dev_config->duty_cycle_pos==0) dev_config->duty_cycle_pos=128;
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dev->host=spihost[host];
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//We want to save a copy of the dev config in the dev struct.
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memcpy(&dev->cfg, dev_config, sizeof(spi_device_interface_config_t));
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//Set CS pin, CS options
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if (dev_config->spics_io_num > 0) {
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if (spihost[host]->no_gpio_matrix &&dev_config->spics_io_num == io_signal[host].spics0_native && freecs==0) {
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//Again, the cs0s for all SPI peripherals map to pin mux source 1, so we use that instead of a define.
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[dev_config->spics_io_num], 1);
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} else {
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//Use GPIO matrix
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[dev_config->spics_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(dev_config->spics_io_num, GPIO_MODE_OUTPUT);
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gpio_matrix_out(dev_config->spics_io_num, io_signal[host].spics_out[freecs], false, false);
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}
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}
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if (dev_config->flags&SPI_DEVICE_CLK_AS_CS) {
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spihost[host]->hw->pin.master_ck_sel |= (1<<freecs);
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} else {
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spihost[host]->hw->pin.master_ck_sel &= (1<<freecs);
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}
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if (dev_config->flags&SPI_DEVICE_POSITIVE_CS) {
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spihost[host]->hw->pin.master_cs_pol |= (1<<freecs);
|
|
} else {
|
|
spihost[host]->hw->pin.master_cs_pol &= (1<<freecs);
|
|
}
|
|
*handle=dev;
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
|
|
{
|
|
int x;
|
|
SPI_CHECK(handle!=NULL, "invalid handle", ESP_ERR_INVALID_ARG);
|
|
//These checks aren't exhaustive; another thread could sneak in a transaction inbetween. These are only here to
|
|
//catch design errors and aren't meant to be triggered during normal operation.
|
|
SPI_CHECK(uxQueueMessagesWaiting(handle->trans_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE);
|
|
SPI_CHECK(handle->host->cur_trans==0 || handle->host->device[handle->host->cur_cs]!=handle, "Have unfinished transactions", ESP_ERR_INVALID_STATE);
|
|
SPI_CHECK(uxQueueMessagesWaiting(handle->ret_queue)==0, "Have unfinished transactions", ESP_ERR_INVALID_STATE);
|
|
|
|
//Kill queues
|
|
vQueueDelete(handle->trans_queue);
|
|
vQueueDelete(handle->ret_queue);
|
|
//Remove device from list of csses and free memory
|
|
for (x=0; x<NO_CS; x++) {
|
|
if (handle->host->device[x] == handle) handle->host->device[x]=NULL;
|
|
}
|
|
free(handle);
|
|
return ESP_OK;
|
|
}
|
|
|
|
static int spi_freq_for_pre_n(int fapb, int pre, int n) {
|
|
return (fapb / (pre * n));
|
|
}
|
|
|
|
static void spi_set_clock(spi_dev_t *hw, int fapb, int hz, int duty_cycle) {
|
|
int pre, n, h, l;
|
|
|
|
//In hw, n, h and l are 1-64, pre is 1-8K. Value written to register is one lower than used value.
|
|
if (hz>((fapb/4)*3)) {
|
|
//Using Fapb directly will give us the best result here.
|
|
hw->clock.clkcnt_l=0;
|
|
hw->clock.clkcnt_h=0;
|
|
hw->clock.clkcnt_n=0;
|
|
hw->clock.clkdiv_pre=0;
|
|
hw->clock.clk_equ_sysclk=1;
|
|
} else {
|
|
//For best duty cycle resolution, we want n to be as close to 32 as possible, but
|
|
//we also need a pre/n combo that gets us as close as possible to the intended freq.
|
|
//To do this, we bruteforce n and calculate the best pre to go along with that.
|
|
//If there's a choice between pre/n combos that give the same result, use the one
|
|
//with the higher n.
|
|
int bestn=-1;
|
|
int bestpre=-1;
|
|
int besterr=0;
|
|
int errval;
|
|
for (n=1; n<=64; n++) {
|
|
//Effectively, this does pre=round((fapb/n)/hz).
|
|
pre=((fapb/n)+(hz/2))/hz;
|
|
if (pre<=0) pre=1;
|
|
if (pre>8192) pre=8192;
|
|
errval=abs(spi_freq_for_pre_n(fapb, pre, n)-hz);
|
|
if (bestn==-1 || errval<=besterr) {
|
|
besterr=errval;
|
|
bestn=n;
|
|
bestpre=pre;
|
|
}
|
|
}
|
|
|
|
n=bestn;
|
|
pre=bestpre;
|
|
l=n;
|
|
//This effectively does round((duty_cycle*n)/256)
|
|
h=(duty_cycle*n+127)/256;
|
|
if (h<=0) h=1;
|
|
|
|
hw->clock.clk_equ_sysclk=0;
|
|
hw->clock.clkcnt_n=n-1;
|
|
hw->clock.clkdiv_pre=pre-1;
|
|
hw->clock.clkcnt_h=h-1;
|
|
hw->clock.clkcnt_l=l-1;
|
|
}
|
|
}
|
|
|
|
|
|
//If a transaction is smaller than or equal to of bits, we do not use DMA; instead, we directly copy/paste
|
|
//bits from/to the work registers. Keep between 32 and (8*32) please.
|
|
#define THRESH_DMA_TRANS (8*32)
|
|
|
|
//This is run in interrupt context and apart from initialization and destruction, this is the only code
|
|
//touching the host (=spihost[x]) variable. The rest of the data arrives in queues. That is why there are
|
|
//no muxes in this code.
|
|
static void IRAM_ATTR spi_intr(void *arg)
|
|
{
|
|
int i;
|
|
int prevCs=-1;
|
|
BaseType_t r;
|
|
BaseType_t do_yield=pdFALSE;
|
|
spi_transaction_t *trans=NULL;
|
|
spi_host_t *host=(spi_host_t*)arg;
|
|
|
|
//Ignore all but the trans_done int.
|
|
if (!host->hw->slave.trans_done) return;
|
|
|
|
if (host->cur_trans) {
|
|
//Okay, transaction is done.
|
|
if ((host->cur_trans->rx_buffer || (host->cur_trans->flags & SPI_TRANS_USE_RXDATA)) && host->cur_trans->rxlength<=THRESH_DMA_TRANS) {
|
|
//Need to copy from SPI regs to result buffer.
|
|
uint32_t *data;
|
|
if (host->cur_trans->flags & SPI_TRANS_USE_RXDATA) {
|
|
data=(uint32_t*)&host->cur_trans->rx_data[0];
|
|
} else {
|
|
data=(uint32_t*)host->cur_trans->rx_buffer;
|
|
}
|
|
for (int x=0; x < host->cur_trans->rxlength; x+=32) {
|
|
//Do a memcpy to get around possible alignment issues in rx_buffer
|
|
uint32_t word=host->hw->data_buf[x/32];
|
|
memcpy(&data[x/32], &word, 4);
|
|
}
|
|
}
|
|
//Call post-transaction callback, if any
|
|
if (host->device[host->cur_cs]->cfg.post_cb) host->device[host->cur_cs]->cfg.post_cb(host->cur_trans);
|
|
//Return transaction descriptor.
|
|
xQueueSendFromISR(host->device[host->cur_cs]->ret_queue, &host->cur_trans, &do_yield);
|
|
host->cur_trans=NULL;
|
|
prevCs=host->cur_cs;
|
|
}
|
|
//ToDo: This is a stupidly simple low-cs-first priority scheme. Make this configurable somehow. - JD
|
|
for (i=0; i<NO_CS; i++) {
|
|
if (host->device[i]) {
|
|
r=xQueueReceiveFromISR(host->device[i]->trans_queue, &trans, &do_yield);
|
|
//Stop looking if we have a transaction to send.
|
|
if (r) break;
|
|
}
|
|
}
|
|
if (i==NO_CS) {
|
|
//No packet waiting. Disable interrupt.
|
|
esp_intr_disable(host->intr);
|
|
} else {
|
|
host->hw->slave.trans_done=0; //clear int bit
|
|
//We have a transaction. Send it.
|
|
spi_device_t *dev=host->device[i];
|
|
host->cur_trans=trans;
|
|
host->cur_cs=i;
|
|
//We should be done with the transmission.
|
|
assert(host->hw->cmd.usr == 0);
|
|
|
|
//Default rxlength to be the same as length, if not filled in.
|
|
if (trans->rxlength==0) {
|
|
trans->rxlength=trans->length;
|
|
}
|
|
|
|
//Reconfigure according to device settings, but only if we change CSses.
|
|
if (i!=prevCs) {
|
|
//Assumes a hardcoded 80MHz Fapb for now. ToDo: figure out something better once we have
|
|
//clock scaling working.
|
|
int apbclk=APB_CLK_FREQ;
|
|
spi_set_clock(host->hw, apbclk, dev->cfg.clock_speed_hz, dev->cfg.duty_cycle_pos);
|
|
//Configure bit order
|
|
host->hw->ctrl.rd_bit_order=(dev->cfg.flags & SPI_DEVICE_RXBIT_LSBFIRST)?1:0;
|
|
host->hw->ctrl.wr_bit_order=(dev->cfg.flags & SPI_DEVICE_TXBIT_LSBFIRST)?1:0;
|
|
|
|
//Configure polarity
|
|
//SPI iface needs to be configured for a delay unless it is not routed through GPIO and clock is >=apb/2
|
|
int nodelay=(host->no_gpio_matrix && dev->cfg.clock_speed_hz >= (apbclk/2));
|
|
if (dev->cfg.mode==0) {
|
|
host->hw->pin.ck_idle_edge=0;
|
|
host->hw->user.ck_out_edge=0;
|
|
host->hw->ctrl2.miso_delay_mode=nodelay?0:2;
|
|
} else if (dev->cfg.mode==1) {
|
|
host->hw->pin.ck_idle_edge=0;
|
|
host->hw->user.ck_out_edge=1;
|
|
host->hw->ctrl2.miso_delay_mode=nodelay?0:1;
|
|
} else if (dev->cfg.mode==2) {
|
|
host->hw->pin.ck_idle_edge=1;
|
|
host->hw->user.ck_out_edge=1;
|
|
host->hw->ctrl2.miso_delay_mode=nodelay?0:1;
|
|
} else if (dev->cfg.mode==3) {
|
|
host->hw->pin.ck_idle_edge=1;
|
|
host->hw->user.ck_out_edge=0;
|
|
host->hw->ctrl2.miso_delay_mode=nodelay?0:2;
|
|
}
|
|
|
|
//Configure bit sizes, load addr and command
|
|
host->hw->user.usr_dummy=(dev->cfg.dummy_bits)?1:0;
|
|
host->hw->user.usr_addr=(dev->cfg.address_bits)?1:0;
|
|
host->hw->user.usr_command=(dev->cfg.command_bits)?1:0;
|
|
host->hw->user1.usr_addr_bitlen=dev->cfg.address_bits-1;
|
|
host->hw->user1.usr_dummy_cyclelen=dev->cfg.dummy_bits-1;
|
|
host->hw->user2.usr_command_bitlen=dev->cfg.command_bits-1;
|
|
//Configure misc stuff
|
|
host->hw->user.doutdin=(dev->cfg.flags & SPI_DEVICE_HALFDUPLEX)?0:1;
|
|
host->hw->user.sio=(dev->cfg.flags & SPI_DEVICE_3WIRE)?1:0;
|
|
|
|
host->hw->ctrl2.setup_time=dev->cfg.cs_ena_pretrans-1;
|
|
host->hw->user.cs_setup=dev->cfg.cs_ena_pretrans?1:0;
|
|
host->hw->ctrl2.hold_time=dev->cfg.cs_ena_posttrans-1;
|
|
host->hw->user.cs_hold=(dev->cfg.cs_ena_posttrans)?1:0;
|
|
|
|
//Configure CS pin
|
|
host->hw->pin.cs0_dis=(i==0)?0:1;
|
|
host->hw->pin.cs1_dis=(i==1)?0:1;
|
|
host->hw->pin.cs2_dis=(i==2)?0:1;
|
|
}
|
|
//Reset DMA
|
|
host->hw->dma_conf.val |= SPI_OUT_RST|SPI_AHBM_RST|SPI_AHBM_FIFO_RST;
|
|
host->hw->dma_out_link.start=0;
|
|
host->hw->dma_in_link.start=0;
|
|
host->hw->dma_conf.val &= ~(SPI_OUT_RST|SPI_AHBM_RST|SPI_AHBM_FIFO_RST);
|
|
//QIO/DIO
|
|
host->hw->ctrl.val &= ~(SPI_FREAD_DUAL|SPI_FREAD_QUAD|SPI_FREAD_DIO|SPI_FREAD_QIO);
|
|
host->hw->user.val &= ~(SPI_FWRITE_DUAL|SPI_FWRITE_QUAD|SPI_FWRITE_DIO|SPI_FWRITE_QIO);
|
|
if (trans->flags & SPI_TRANS_MODE_DIO) {
|
|
if (trans->flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
|
|
host->hw->ctrl.fread_dio=1;
|
|
host->hw->user.fwrite_dio=1;
|
|
} else {
|
|
host->hw->ctrl.fread_dual=1;
|
|
host->hw->user.fwrite_dual=1;
|
|
}
|
|
host->hw->ctrl.fastrd_mode=1;
|
|
} else if (trans->flags & SPI_TRANS_MODE_QIO) {
|
|
if (trans->flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
|
|
host->hw->ctrl.fread_qio=1;
|
|
host->hw->user.fwrite_qio=1;
|
|
} else {
|
|
host->hw->ctrl.fread_quad=1;
|
|
host->hw->user.fwrite_quad=1;
|
|
}
|
|
host->hw->ctrl.fastrd_mode=1;
|
|
}
|
|
|
|
|
|
//Fill DMA descriptors
|
|
if (trans->rx_buffer || (trans->flags & SPI_TRANS_USE_RXDATA)) {
|
|
uint32_t *data;
|
|
if (trans->flags & SPI_TRANS_USE_RXDATA) {
|
|
data=(uint32_t *)&trans->rx_data[0];
|
|
} else {
|
|
data=trans->rx_buffer;
|
|
}
|
|
if (trans->rxlength<THRESH_DMA_TRANS) {
|
|
//No need for DMA; we'll copy the result out of the work registers directly later.
|
|
} else {
|
|
host->hw->user.usr_miso_highpart=0;
|
|
host->dmadesc_rx.size=(trans->rxlength+7)/8;
|
|
host->dmadesc_rx.length=(trans->rxlength+7)/8;
|
|
host->dmadesc_rx.buf=(uint8_t*)data;
|
|
host->dmadesc_rx.eof=1;
|
|
host->dmadesc_rx.sosf=0;
|
|
host->dmadesc_rx.owner=1;
|
|
host->hw->dma_in_link.addr=(int)(&host->dmadesc_rx)&0xFFFFF;
|
|
host->hw->dma_in_link.start=1;
|
|
}
|
|
host->hw->user.usr_miso=1;
|
|
} else {
|
|
host->hw->user.usr_miso=0;
|
|
}
|
|
|
|
if (trans->tx_buffer || (trans->flags & SPI_TRANS_USE_TXDATA)) {
|
|
uint32_t *data;
|
|
if (trans->flags & SPI_TRANS_USE_TXDATA) {
|
|
data=(uint32_t *)&trans->tx_data[0];
|
|
} else {
|
|
data=(uint32_t *)trans->tx_buffer;
|
|
}
|
|
if (trans->rxlength < 8*32) {
|
|
//No need for DMA.
|
|
for (int x=0; x < trans->rxlength; x+=32) {
|
|
//Use memcpy to get around alignment issues for txdata
|
|
uint32_t word;
|
|
memcpy(&word, &data[x/32], 4);
|
|
host->hw->data_buf[(x/32)+8]=word;
|
|
}
|
|
host->hw->user.usr_mosi_highpart=1;
|
|
} else {
|
|
host->hw->user.usr_mosi_highpart=0;
|
|
host->dmadesc_tx.size=(trans->length+7)/8;
|
|
host->dmadesc_tx.length=(trans->length+7)/8;
|
|
host->dmadesc_tx.buf=(uint8_t*)data;
|
|
host->dmadesc_tx.eof=1;
|
|
host->dmadesc_tx.sosf=0;
|
|
host->dmadesc_tx.owner=1;
|
|
host->hw->dma_out_link.addr=(int)(&host->dmadesc_tx) & 0xFFFFF;
|
|
host->hw->dma_out_link.start=1;
|
|
}
|
|
}
|
|
host->hw->mosi_dlen.usr_mosi_dbitlen=trans->length-1;
|
|
host->hw->miso_dlen.usr_miso_dbitlen=trans->rxlength-1;
|
|
host->hw->user2.usr_command_value=trans->command;
|
|
if (dev->cfg.address_bits>32) {
|
|
host->hw->addr=trans->address >> 32;
|
|
host->hw->slv_wr_status=trans->address & 0xffffffff;
|
|
} else {
|
|
host->hw->addr=trans->address & 0xffffffff;
|
|
}
|
|
host->hw->user.usr_mosi=(trans->tx_buffer==NULL)?0:1;
|
|
host->hw->user.usr_miso=(trans->tx_buffer==NULL)?0:1;
|
|
|
|
//Call pre-transmission callback, if any
|
|
if (dev->cfg.pre_cb) dev->cfg.pre_cb(trans);
|
|
//Kick off transfer
|
|
host->hw->cmd.usr=1;
|
|
}
|
|
if (do_yield) portYIELD_FROM_ISR();
|
|
}
|
|
|
|
|
|
esp_err_t spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait)
|
|
{
|
|
BaseType_t r;
|
|
SPI_CHECK(handle!=NULL, "invalid dev handle", ESP_ERR_INVALID_ARG);
|
|
SPI_CHECK((trans_desc->flags & SPI_TRANS_USE_RXDATA)==0 ||trans_desc->length <= 32, "rxdata transfer > 32bytes", ESP_ERR_INVALID_ARG);
|
|
SPI_CHECK((trans_desc->flags & SPI_TRANS_USE_TXDATA)==0 ||trans_desc->length <= 32, "txdata transfer > 32bytes", ESP_ERR_INVALID_ARG);
|
|
SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO|SPI_TRANS_MODE_QIO)) && (handle->cfg.flags & SPI_DEVICE_3WIRE)), "incompatible iface params", ESP_ERR_INVALID_ARG);
|
|
SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO|SPI_TRANS_MODE_QIO)) && (!(handle->cfg.flags & SPI_DEVICE_HALFDUPLEX))), "incompatible iface params", ESP_ERR_INVALID_ARG);
|
|
r=xQueueSend(handle->trans_queue, (void*)&trans_desc, ticks_to_wait);
|
|
if (!r) return ESP_ERR_TIMEOUT;
|
|
esp_intr_enable(handle->host->intr);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t spi_device_get_trans_result(spi_device_handle_t handle, spi_transaction_t **trans_desc, TickType_t ticks_to_wait)
|
|
{
|
|
BaseType_t r;
|
|
SPI_CHECK(handle!=NULL, "invalid dev handle", ESP_ERR_INVALID_ARG);
|
|
r=xQueueReceive(handle->ret_queue, (void*)trans_desc, ticks_to_wait);
|
|
if (!r) return ESP_ERR_TIMEOUT;
|
|
return ESP_OK;
|
|
}
|
|
|
|
//Porcelain to do one blocking transmission.
|
|
esp_err_t spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc)
|
|
{
|
|
esp_err_t ret;
|
|
spi_transaction_t *ret_trans;
|
|
//ToDo: check if any spi transfers in flight
|
|
ret=spi_device_queue_trans(handle, trans_desc, portMAX_DELAY);
|
|
if (ret!=ESP_OK) return ret;
|
|
ret=spi_device_get_trans_result(handle, &ret_trans, portMAX_DELAY);
|
|
if (ret!=ESP_OK) return ret;
|
|
assert(ret_trans==trans_desc);
|
|
return ESP_OK;
|
|
}
|
|
|