fdf983e0c4
The SPI bus lock on SPI1 introduces two side effects:
1. The device lock for the main flash requires the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` to be selected, however this
option is disabled by default in earlier IDF versions. Some developers
may find their project cannot be built by their old sdkconfig files.
2. Usually we don't need the lock on the SPI1 bus, due to it's
restrictions. However the overhead still exists in this case, the IRAM
cost for static version of semaphore functions, and the time cost when
getting and releasing the lock.
This commit:
1. Add a CONFIG_SPI_FLASH_BYPASS_MAIN_LOCK option, which will forbid the
space cost, as well as the initialization of the main bus lock.
2. When the option is not selected, the bus lock is used, the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` will be selected explicitly.
3. Revert default value of `CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION`
to `n`.
introduced in 49a48644e4.
Closes https://github.com/espressif/esp-idf/issues/5046
347 lines
No EOL
11 KiB
C
347 lines
No EOL
11 KiB
C
#include "sdkconfig.h"
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#include "esp_log.h"
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#include "driver/spi_master.h"
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#include "driver/gpio.h"
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#include "esp_flash_spi_init.h"
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#include "test/test_common_spi.h"
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#include "unity.h"
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#if CONFIG_IDF_TARGET_ESP32
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// The VSPI pins on UT_T1_ESP_FLASH are connected to a external flash
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#define TEST_BUS_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO
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#define TEST_BUS_PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI
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#define TEST_BUS_PIN_NUM_CLK VSPI_IOMUX_PIN_NUM_CLK
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#define TEST_BUS_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS
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#define TEST_BUS_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
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#define TEST_BUS_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define TEST_BUS_PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
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#define TEST_BUS_PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
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#define TEST_BUS_PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
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#define TEST_BUS_PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
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#define TEST_BUS_PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
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#define TEST_BUS_PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
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#endif
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typedef struct {
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union {
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spi_device_handle_t handle;
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esp_flash_t* chip;
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};
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bool finished;
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} task_context_t;
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#ifndef CONFIG_ESP32_SPIRAM_SUPPORT
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const static char TAG[] = "test_spi";
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void spi_task1(void* arg)
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{
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//task1 send 50 polling transactions, acquire the bus and send another 50
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int count=0;
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spi_transaction_t t = {
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.flags = SPI_TRANS_USE_TXDATA,
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.tx_data = { 0x80, 0x12, 0x34, 0x56 },
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.length = 4*8,
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};
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spi_device_handle_t handle = ((task_context_t*)arg)->handle;
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for( int j = 0; j < 50; j ++ ) {
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TEST_ESP_OK(spi_device_polling_transmit( handle, &t ));
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ESP_LOGI(TAG, "task1:%d", count++ );
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}
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TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY ));
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for( int j = 0; j < 50; j ++ ) {
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TEST_ESP_OK(spi_device_polling_transmit( handle, &t ));
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ESP_LOGI(TAG, "task1:%d", count++ );
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}
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spi_device_release_bus(handle);
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ESP_LOGI(TAG, "task1 terminates");
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((task_context_t*)arg)->finished = true;
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vTaskDelete(NULL);
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}
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void spi_task2(void* arg)
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{
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int count=0;
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//task2 acquire the bus, send 50 polling transactions and then 50 non-polling
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spi_transaction_t t = {
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.flags = SPI_TRANS_USE_TXDATA,
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.tx_data = { 0x80, 0x12, 0x34, 0x56 },
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.length = 4*8,
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};
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spi_transaction_t *ret_t;
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spi_device_handle_t handle = ((task_context_t*)arg)->handle;
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TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY ));
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for (int i = 0; i < 50; i ++) {
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TEST_ESP_OK(spi_device_polling_transmit(handle, &t));
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ESP_LOGI( TAG, "task2: %d", count++ );
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}
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for( int j = 0; j < 50; j ++ ) {
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TEST_ESP_OK(spi_device_queue_trans(handle, &t, portMAX_DELAY));
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}
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for( int j = 0; j < 50; j ++ ) {
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TEST_ESP_OK(spi_device_get_trans_result(handle, &ret_t, portMAX_DELAY));
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assert(ret_t == &t);
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ESP_LOGI( TAG, "task2: %d", count++ );
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}
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spi_device_release_bus(handle);
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vTaskDelay(1);
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ESP_LOGI(TAG, "task2 terminates");
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((task_context_t*)arg)->finished = true;
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vTaskDelete(NULL);
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}
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void spi_task3(void* arg)
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{
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//task3 send 30 polling transactions, acquire the bus, send 20 polling transactions and then 50 non-polling
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int count=0;
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spi_transaction_t t = {
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.flags = SPI_TRANS_USE_TXDATA,
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.tx_data = { 0x80, 0x12, 0x34, 0x56 },
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.length = 4*8,
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};
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spi_transaction_t *ret_t;
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spi_device_handle_t handle = ((task_context_t*)arg)->handle;
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for (int i = 0; i < 30; i ++) {
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TEST_ESP_OK(spi_device_polling_transmit(handle, &t));
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ESP_LOGI( TAG, "task3: %d", count++ );
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}
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TEST_ESP_OK(spi_device_acquire_bus( handle, portMAX_DELAY ));
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for (int i = 0; i < 20; i ++) {
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TEST_ESP_OK(spi_device_polling_transmit(handle, &t));
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ESP_LOGI( TAG, "task3: %d", count++ );
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}
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for (int j = 0; j < 50; j++) {
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TEST_ESP_OK(spi_device_queue_trans(handle, &t, portMAX_DELAY));
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}
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for (int j = 0; j < 50; j++) {
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TEST_ESP_OK(spi_device_get_trans_result(handle, &ret_t, portMAX_DELAY));
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assert(ret_t == &t);
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ESP_LOGI(TAG, "task3: %d", count++);
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}
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spi_device_release_bus(handle);
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ESP_LOGI(TAG, "task3 terminates");
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((task_context_t*)arg)->finished = true;
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vTaskDelete(NULL);
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}
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static void write_large_buffer(esp_flash_t *chip, const esp_partition_t *part, const uint8_t *source, size_t length)
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{
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printf("Erasing chip %p, %d bytes\n", chip, length);
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TEST_ESP_OK(esp_flash_erase_region(chip, part->address, (length + SPI_FLASH_SEC_SIZE) & ~(SPI_FLASH_SEC_SIZE - 1)) );
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printf("Writing chip %p, %d bytes from source %p\n", chip, length, source);
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// note writing to unaligned address
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TEST_ESP_OK(esp_flash_write(chip, source, part->address + 1, length) );
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printf("Write done.\n");
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}
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static void read_and_check(esp_flash_t *chip, const esp_partition_t *part, const uint8_t *source, size_t length)
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{
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printf("Checking chip %p, %d bytes\n", chip, length);
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uint8_t *buf = malloc(length);
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TEST_ASSERT_NOT_NULL(buf);
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TEST_ESP_OK(esp_flash_read(chip, buf, part->address + 1, length) );
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TEST_ASSERT_EQUAL_HEX8_ARRAY(source, buf, length);
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free(buf);
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// check nothing was written at beginning or end
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uint8_t ends[8];
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TEST_ESP_OK(esp_flash_read(chip, ends, part->address, sizeof(ends)) );
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TEST_ASSERT_EQUAL_HEX8(0xFF, ends[0]);
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TEST_ASSERT_EQUAL_HEX8(source[0], ends[1]);
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TEST_ESP_OK(esp_flash_read(chip, ends, part->address + length, sizeof(ends)) );
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TEST_ASSERT_EQUAL_HEX8(source[length - 1], ends[0]);
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TEST_ASSERT_EQUAL_HEX8(0xFF, ends[1]);
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TEST_ASSERT_EQUAL_HEX8(0xFF, ends[2]);
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TEST_ASSERT_EQUAL_HEX8(0xFF, ends[3]);
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}
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void spi_task4(void* arg)
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{
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esp_flash_t *chip = ((task_context_t*)arg)->chip;
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// buffer in RAM
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const int test_len = 16400;
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uint8_t *source_buf = heap_caps_malloc(test_len, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(source_buf);
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srand(676);
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for (int i = 0; i < test_len; i++) {
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source_buf[i] = rand();
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}
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ESP_LOGI(TAG, "Testing chip %p...", chip);
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const esp_partition_t *part = get_test_data_partition();
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TEST_ASSERT(part->size > test_len + 2 + SPI_FLASH_SEC_SIZE);
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write_large_buffer(chip, part, source_buf, test_len);
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read_and_check(chip, part, source_buf, test_len);
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free(source_buf);
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ESP_LOGI(TAG, "task4 terminates");
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((task_context_t*)arg)->finished = true;
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vTaskDelete(NULL);
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}
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static void test_bus_lock(bool test_flash)
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{
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task_context_t context1={};
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task_context_t context2={};
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task_context_t context3={};
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task_context_t context4={};
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TaskHandle_t task1, task2, task3, task4;
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esp_err_t ret;
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spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
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buscfg.miso_io_num = TEST_BUS_PIN_NUM_MISO;
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buscfg.mosi_io_num = TEST_BUS_PIN_NUM_MOSI;
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buscfg.sclk_io_num = TEST_BUS_PIN_NUM_CLK;
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spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG();
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devcfg.queue_size = 100;
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//Initialize the SPI bus and 3 devices
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ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1);
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TEST_ESP_OK(ret);
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ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context1.handle);
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TEST_ESP_OK(ret);
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ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context2.handle);
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TEST_ESP_OK(ret);
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//only have 3 cs pins, leave one for the flash
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devcfg.spics_io_num = -1;
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ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context3.handle);
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TEST_ESP_OK(ret);
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esp_flash_spi_device_config_t flash_cfg = {
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.host_id = TEST_SPI_HOST,
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.cs_id = 2,
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.cs_io_num = TEST_BUS_PIN_NUM_CS,
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.io_mode = SPI_FLASH_DIO,
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.speed = ESP_FLASH_5MHZ,
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.input_delay_ns = 0,
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};
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//Clamp the WP and HD pins to VDD to make it work in DIO mode
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gpio_set_direction(TEST_BUS_PIN_NUM_HD, GPIO_MODE_OUTPUT);
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gpio_set_direction(TEST_BUS_PIN_NUM_WP, GPIO_MODE_OUTPUT);
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gpio_set_level(TEST_BUS_PIN_NUM_HD, 1);
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gpio_set_level(TEST_BUS_PIN_NUM_WP, 1);
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esp_flash_t *chip;
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(void) chip;
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if (test_flash) {
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ret = spi_bus_add_flash_device(&chip, &flash_cfg);
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TEST_ESP_OK(ret);
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ret = esp_flash_init(chip);
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TEST_ESP_OK(ret);
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context4.chip = chip;
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}
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ESP_LOGI(TAG, "Start testing...");
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xTaskCreate( spi_task1, "task1", 2048, &context1, 0, &task1 );
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xTaskCreate( spi_task2, "task2", 2048, &context2, 0, &task2 );
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xTaskCreate( spi_task3, "task3", 2048, &context3, 0, &task3 );
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if (test_flash) {
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xTaskCreate( spi_task4, "task4", 2048, &context4, 0, &task4 );
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} else {
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context4.finished = true;
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}
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for(;;){
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vTaskDelay(10);
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if (context1.finished && context2.finished && context3.finished && context4.finished) break;
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}
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TEST_ESP_OK(spi_bus_remove_device(context1.handle));
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TEST_ESP_OK(spi_bus_remove_device(context2.handle));
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TEST_ESP_OK(spi_bus_remove_device(context3.handle));
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if (test_flash) {
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TEST_ESP_OK(spi_bus_remove_flash_device(chip));
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}
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TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST) );
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}
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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//no runners
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TEST_CASE("spi bus lock, with flash","[spi][test_env=UT_T1_ESP_FLASH]")
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{
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test_bus_lock(true);
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}
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#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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TEST_CASE("spi bus lock","[spi]")
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{
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test_bus_lock(false);
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}
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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//SPI1 not supported by driver
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static IRAM_ATTR esp_err_t test_polling_send(spi_device_handle_t handle)
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{
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for (int i = 0; i < 10; i++) {
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spi_transaction_t trans = {
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.length = 16,
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.flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA,
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};
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esp_err_t err = spi_device_polling_transmit(handle, &trans);
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if (err != ESP_OK) {
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return err;
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}
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}
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return ESP_OK;
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}
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static IRAM_ATTR NOINLINE_ATTR void test_acquire(spi_device_handle_t handle)
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{
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esp_err_t err = spi_device_acquire_bus(handle, portMAX_DELAY);
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if (err == ESP_OK) {
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err = test_polling_send(handle);
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spi_device_release_bus(handle);
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}
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TEST_ESP_OK(err);
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}
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TEST_CASE("spi master can be used on SPI1", "[spi]")
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{
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spi_device_interface_config_t dev_cfg = {
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.mode = 1,
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.clock_speed_hz = 1*1000*1000,
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.spics_io_num = -1,
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.queue_size = 1,
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};
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spi_device_handle_t handle;
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esp_err_t err;
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err = spi_bus_add_device(SPI1_HOST, &dev_cfg, &handle);
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TEST_ESP_OK(err);
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err = test_polling_send(handle);
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TEST_ESP_OK(err);
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test_acquire(handle);
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err = spi_bus_remove_device(handle);
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TEST_ESP_OK(err);
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}
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#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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//TODO: add a case when a non-polling transaction happened in the bus-acquiring time and then release the bus then queue a new trans
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#endif |