226 lines
No EOL
7.2 KiB
C
226 lines
No EOL
7.2 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <string.h>
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#include "ccomp_timer_impl.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "eri.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_freertos_hooks.h"
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#include "perfmon.h"
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#include "xtensa/core-macros.h"
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#include "xtensa/xt_perf_consts.h"
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#include "xtensa-debug-module.h"
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#include "esp_ipc.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/clk.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/clk.h"
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#endif
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#define D_STALL_COUNTER_ID 0
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#define I_STALL_COUNTER_ID 1
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typedef enum
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{
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PERF_TIMER_UNINIT = 0, // timer has not been initialized yet
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PERF_TIMER_IDLE, // timer has been initialized but is not tracking elapsed time
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PERF_TIMER_ACTIVE // timer is tracking elapsed time
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} ccomp_timer_state_t;
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typedef struct
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{
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int i_ovfl; // number of times instruction stall counter has overflowed
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int d_ovfl; // number of times data stall counter has overflowed
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uint32_t last_ccount; // last CCOUNT value, updated every os tick
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ccomp_timer_state_t state; // state of the timer
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intr_handle_t intr_handle; // handle to allocated handler for perfmon counter overflows, so that it can be freed during deinit
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int64_t ccount; // accumulated processors cycles during the time when timer is active
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} ccomp_timer_status_t;
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// Each core has its independent timer
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ccomp_timer_status_t s_status[] = {
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(ccomp_timer_status_t){
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.i_ovfl = 0,
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.d_ovfl = 0,
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.ccount = 0,
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.last_ccount = 0,
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.state = PERF_TIMER_UNINIT,
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.intr_handle = NULL,
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},
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(ccomp_timer_status_t){
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.i_ovfl = 0,
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.d_ovfl = 0,
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.ccount = 0,
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.last_ccount = 0,
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.state = PERF_TIMER_UNINIT,
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.intr_handle = NULL
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}
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};
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static portMUX_TYPE s_lock = portMUX_INITIALIZER_UNLOCKED;
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static void IRAM_ATTR update_ccount(void)
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{
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if (s_status[xPortGetCoreID()].state == PERF_TIMER_ACTIVE) {
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int64_t new_ccount = xthal_get_ccount();
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if (new_ccount > s_status[xPortGetCoreID()].last_ccount) {
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s_status[xPortGetCoreID()].ccount += new_ccount - s_status[xPortGetCoreID()].last_ccount;
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} else {
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// CCOUNT has wrapped around
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s_status[xPortGetCoreID()].ccount += new_ccount + (UINT32_MAX - s_status[xPortGetCoreID()].last_ccount);
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}
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s_status[xPortGetCoreID()].last_ccount = new_ccount;
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}
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}
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static void inline update_overflow(int id, int *cnt)
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{
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uint32_t pmstat = eri_read(ERI_PERFMON_PMSTAT0 + id * sizeof(int32_t));
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if (pmstat & PMSTAT_OVFL) {
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*cnt += 1;
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// Clear overflow and PerfMonInt asserted bits. The only valid bits in PMSTAT is the ones we're trying to clear. So it should be
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// ok to just modify the whole register.
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eri_write(ERI_PERFMON_PMSTAT0 + id, ~0x0);
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}
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}
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static void IRAM_ATTR perf_counter_overflow_handler(void *args)
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{
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update_overflow(D_STALL_COUNTER_ID, &s_status[xPortGetCoreID()].d_ovfl);
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update_overflow(I_STALL_COUNTER_ID, &s_status[xPortGetCoreID()].i_ovfl);
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}
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static void set_perfmon_interrupt(bool enable)
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{
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uint32_t d_pmctrl = eri_read(ERI_PERFMON_PMCTRL0 + D_STALL_COUNTER_ID * sizeof(int32_t));
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uint32_t i_pmctrl = eri_read(ERI_PERFMON_PMCTRL0 + I_STALL_COUNTER_ID * sizeof(int32_t));
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if (enable) {
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d_pmctrl |= PMCTRL_INTEN;
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i_pmctrl |= PMCTRL_INTEN;
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}
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else {
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d_pmctrl &= ~PMCTRL_INTEN;
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i_pmctrl &= ~PMCTRL_INTEN;
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}
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eri_write(ERI_PERFMON_PMCTRL0 + D_STALL_COUNTER_ID * sizeof(int32_t), d_pmctrl);
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eri_write(ERI_PERFMON_PMCTRL0 + I_STALL_COUNTER_ID * sizeof(int32_t), i_pmctrl);
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}
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esp_err_t ccomp_timer_impl_init(void)
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{
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// Keep track of how many times each counter has overflowed.
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esp_err_t err = esp_intr_alloc(ETS_INTERNAL_PROFILING_INTR_SOURCE, 0,
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perf_counter_overflow_handler, NULL, &s_status[xPortGetCoreID()].intr_handle);
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if (err != ESP_OK) {
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return err;
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}
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xtensa_perfmon_init(D_STALL_COUNTER_ID,
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XTPERF_CNT_D_STALL,
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XTPERF_MASK_D_STALL_BUSY, 0, -1);
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xtensa_perfmon_init(I_STALL_COUNTER_ID,
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XTPERF_CNT_I_STALL,
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XTPERF_MASK_I_STALL_BUSY, 0, -1);
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set_perfmon_interrupt(true);
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s_status[xPortGetCoreID()].state = PERF_TIMER_IDLE;
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return ESP_OK;
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}
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esp_err_t ccomp_timer_impl_deinit(void)
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{
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set_perfmon_interrupt(false);
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esp_err_t err = esp_intr_free(s_status[xPortGetCoreID()].intr_handle);
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if (err != ESP_OK) {
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return err;
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}
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s_status[xPortGetCoreID()].intr_handle = NULL;
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s_status[xPortGetCoreID()].state = PERF_TIMER_UNINIT;
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return ESP_OK;
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}
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esp_err_t ccomp_timer_impl_start(void)
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{
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s_status[xPortGetCoreID()].state = PERF_TIMER_ACTIVE;
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s_status[xPortGetCoreID()].last_ccount = xthal_get_ccount();
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// Update elapsed cycles every OS tick
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esp_register_freertos_tick_hook_for_cpu(update_ccount, xPortGetCoreID());
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xtensa_perfmon_start();
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return ESP_OK;
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}
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esp_err_t IRAM_ATTR ccomp_timer_impl_stop(void)
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{
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xtensa_perfmon_stop();
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esp_deregister_freertos_tick_hook_for_cpu(update_ccount, xPortGetCoreID());
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update_ccount();
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s_status[xPortGetCoreID()].state = PERF_TIMER_IDLE;
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return ESP_OK;
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}
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int64_t IRAM_ATTR ccomp_timer_impl_get_time(void)
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{
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update_ccount();
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int64_t d_stalls = xtensa_perfmon_value(D_STALL_COUNTER_ID) +
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s_status[xPortGetCoreID()].d_ovfl * (1 << sizeof(int32_t));
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int64_t i_stalls = xtensa_perfmon_value(I_STALL_COUNTER_ID) +
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s_status[xPortGetCoreID()].i_ovfl * (1 << sizeof(int32_t));
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int64_t stalls = d_stalls + i_stalls;
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int64_t cycles = s_status[xPortGetCoreID()].ccount;
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return ((cycles - stalls) * 1000000) / esp_clk_cpu_freq();
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}
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esp_err_t ccomp_timer_impl_reset(void)
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{
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xtensa_perfmon_reset(D_STALL_COUNTER_ID);
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xtensa_perfmon_reset(I_STALL_COUNTER_ID);
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s_status[xPortGetCoreID()].d_ovfl = 0;
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s_status[xPortGetCoreID()].i_ovfl = 0;
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s_status[xPortGetCoreID()].ccount = 0;
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s_status[xPortGetCoreID()].last_ccount = 0;
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return ESP_OK;
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}
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bool ccomp_timer_impl_is_init(void)
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{
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return s_status[xPortGetCoreID()].state != PERF_TIMER_UNINIT;
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}
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bool IRAM_ATTR ccomp_timer_impl_is_active(void)
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{
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return s_status[xPortGetCoreID()].state == PERF_TIMER_ACTIVE;
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}
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void IRAM_ATTR ccomp_timer_impl_lock(void)
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{
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portENTER_CRITICAL(&s_lock);
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}
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void IRAM_ATTR ccomp_timer_impl_unlock(void)
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{
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portEXIT_CRITICAL(&s_lock);
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} |