Ivan Grokhotkov b6113eb73b bootloader: account for load address when mapping cache pages ... Bootloader used to calculate the number of cache pages assuming that load address was aligned, while in reality load address for DROM and IROM was offset by 0x20 bytes from the start of 64kB page. This caused the bootloader to map one less page if the size of the image was 0x4..0x1c less than a multiple of 64kB. Reported in https://esp32.com/viewtopic.php?f=13&t=6952.		2019-01-23 17:13:30 +08:00
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bootloader_config.h	bootloader: Fallback if OTA data is invalid	2017-08-15 09:42:19 +10:00
bootloader_start.c	bootloader: account for load address when mapping cache pages	2019-01-23 17:13:30 +08:00
component.mk	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00
esp32.bootloader.ld	bootloader: verify that loaded image does not overlap bootloader code	2018-10-30 17:35:23 +08:00
esp32.bootloader.rom.ld	build system: Use component.mk for all components, refactor bootloader build	2017-07-19 09:10:48 +10:00
flash_qio_mode.c	feature(flash): support for QIO mode of XM25QU64A	2018-08-08 03:39:19 +00:00
flash_qio_mode.h	build system: Use component.mk for all components, refactor bootloader build	2017-07-19 09:10:48 +10:00
Makefile.projbuild	Revert "bootloader: Add option to build with Link Time Optimisation enabled"	2017-07-24 05:14:31 +08:00