39ddc7b836
1) PS is fixed up to allow GDB backtrace to work properly 2) MR!341 discussion: in core dump module: esp_panicPutXXX was replaced by ets_printf. 3) MR!341 discussion: core dump flash magic number was changed. 4) MR!341 discussion: SPI flash access API was redesigned to allow flexible critical section management. 5) test app for core dump feature was added 6) fixed base64 file reading issues on Windows platform 7) now raw bin core file is deleted upon core loader failure by epscoredump.py
54 lines
2.1 KiB
C
54 lines
2.1 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef ESP_SPI_FLASH_CACHE_UTILS_H
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#define ESP_SPI_FLASH_CACHE_UTILS_H
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/**
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* This header file contains declarations of cache manipulation functions
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* used both in flash_ops.c and flash_mmap.c.
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*
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* These functions are considered internal and are not designed to be called from applications.
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*/
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// Init mutex protecting access to spi_flash_* APIs
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void spi_flash_init_lock();
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// Take mutex protecting access to spi_flash_* APIs
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void spi_flash_op_lock();
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// Release said mutex
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void spi_flash_op_unlock();
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// Suspend the scheduler on both CPUs, disable cache.
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// Contrary to its name this doesn't do anything with interrupts, yet.
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// Interrupt disabling capability will be added once we implement
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// interrupt allocation API.
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void spi_flash_disable_interrupts_caches_and_other_cpu();
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// Enable cache, enable interrupts (to be added in future), resume scheduler
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void spi_flash_enable_interrupts_caches_and_other_cpu();
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// Disables non-IRAM interrupt handlers on current CPU and caches on both CPUs.
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// This function is implied to be called from panic handler or when no OS is present
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// when non-current CPU is halted and can not execute code from flash.
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void spi_flash_disable_interrupts_caches_and_other_cpu_no_os();
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// Enable cache, enable interrupts (to be added in future) on current CPU.
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// This function is implied to be called from panic handler or when no OS is present
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// when non-current CPU is halted and can not execute code from flash.
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void spi_flash_enable_interrupts_caches_no_os();
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#endif //ESP_SPI_FLASH_CACHE_UTILS_H
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