149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
/* xer-constants.h -- various constants describing external registers accessed
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via wer and rer.
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TODO: find a better prefix. Also conditionalize certain constants based
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on number of cores and interrupts actually present.
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*/
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/*
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* Copyright (c) 1999-2008 Tensilica Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <xtensa/config/core.h>
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#define NUM_INTERRUPTS 27
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#define NUM_CORES 4
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/* Routing of NMI (BInterrupt2) and interrupts 0..n-1 (BInterrupt3+)
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RER reads
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WER writes
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*/
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#define XER_MIROUT 0x0000
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#define XER_MIROUT_LAST (XER_MIROUT + NUM_INTERRUPTS)
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/* IPI to core M (all 16 causes).
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RER reads
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WER clears
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*/
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#define XER_MIPICAUSE 0x0100
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#define XER_MIPICAUSE_FIELD_A_FIRST 0x0
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#define XER_MIPICAUSE_FIELD_A_LAST 0x0
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#define XER_MIPICAUSE_FIELD_B_FIRST 0x1
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#define XER_MIPICAUSE_FIELD_B_LAST 0x3
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#define XER_MIPICAUSE_FIELD_C_FIRST 0x4
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#define XER_MIPICAUSE_FIELD_C_LAST 0x7
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#define XER_MIPICAUSE_FIELD_D_FIRST 0x8
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#define XER_MIPICAUSE_FIELD_D_LAST 0xF
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/* IPI from cause bit 0..15
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RER invalid
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WER sets
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*/
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#define XER_MIPISET 0x0140
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#define XER_MIPISET_LAST 0x014F
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/* Global enable
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RER read
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WER clear
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*/
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#define XER_MIENG 0x0180
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/* Global enable
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RER invalid
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WER set
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*/
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#define XER_MIENG_SET 0x0184
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/* Global assert
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RER read
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WER clear
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*/
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#define XER_MIASG 0x0188
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/* Global enable
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RER invalid
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WER set
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*/
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#define XER_MIASG_SET 0x018C
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/* IPI partition register
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RER read
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WER write
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*/
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#define XER_PART 0x0190
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#define XER_IPI0 0x0
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#define XER_IPI1 0x1
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#define XER_IPI2 0x2
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#define XER_IPI3 0x3
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#define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2))
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#define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D) \
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(XER_PART_ROUTE_IPI(TO_A, XER_IPI0) | \
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XER_PART_ROUTE_IPI(TO_B, XER_IPI1) | \
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XER_PART_ROUTE_IPI(TO_C, XER_IPI2) | \
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XER_PART_ROUTE_IPI(TO_D, XER_IPI3))
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#define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM
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#define XER_IPI_WAKE_CAUSE XER_MIPICAUSE_FIELD_C_FIRST
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#define XER_IPI_WAKE_ADDRESS (XER_MIPISET + XER_IPI_WAKE_CAUSE)
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#define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3)
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/* System configuration ID
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RER read
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WER invalid
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*/
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#define XER_SYSCFGID 0x01A0
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/* RunStall to slave processors
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RER read
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WER write
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*/
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#define XER_MPSCORE 0x0200
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/* Cache coherency ON
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RER read
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WER write
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*/
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#define XER_CCON 0x0220
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