7528dc0f20
1. Add support for new PHY IP101. 2. Re-enable GPIO0 output mode. 3. Clean up some docs.
124 lines
2.9 KiB
C
124 lines
2.9 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _EMAC_COMMON_H_
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#define _EMAC_COMMON_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "esp_eth.h"
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#include "emac_dev.h"
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typedef uint32_t emac_sig_t;
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typedef uint32_t emac_par_t;
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typedef struct {
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emac_sig_t sig;
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emac_par_t par;
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} emac_event_t;
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enum emac_runtime_status {
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EMAC_RUNTIME_NOT_INIT = 0,
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EMAC_RUNTIME_INIT,
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EMAC_RUNTIME_START,
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EMAC_RUNTIME_STOP,
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};
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enum {
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SIG_EMAC_RX_UNAVAIL,
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SIG_EMAC_TX_DONE,
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SIG_EMAC_RX_DONE,
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SIG_EMAC_START,
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SIG_EMAC_STOP,
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SIG_EMAC_CHECK_LINK,
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SIG_EMAC_MAX
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};
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struct emac_config_data {
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eth_phy_base_t phy_addr;
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eth_mode_t mac_mode;
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eth_clock_mode_t clock_mode;
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struct dma_extended_desc *dma_etx;
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uint32_t cur_tx;
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uint32_t dirty_tx;
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int32_t cnt_tx;
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struct dma_extended_desc *dma_erx;
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uint32_t cur_rx;
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uint32_t dirty_rx;
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int32_t cnt_rx;
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uint32_t rx_need_poll;
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bool phy_link_up;
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enum emac_runtime_status emac_status;
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uint8_t macaddr[6];
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eth_phy_func phy_init;
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eth_tcpip_input_func emac_tcpip_input;
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eth_gpio_config_func emac_gpio_config;
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eth_phy_check_link_func emac_phy_check_link;
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eth_phy_check_init_func emac_phy_check_init;
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eth_phy_get_speed_mode_func emac_phy_get_speed_mode;
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eth_phy_get_duplex_mode_func emac_phy_get_duplex_mode;
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bool emac_flow_ctrl_enable;
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bool emac_flow_ctrl_partner_support;
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eth_phy_get_partner_pause_enable_func emac_phy_get_partner_pause_enable;
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eth_phy_power_enable_func emac_phy_power_enable;
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uint32_t reset_timeout_ms;
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};
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enum emac_post_type {
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EMAC_POST_ASYNC,
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EMAC_POST_SYNC,
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};
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struct emac_post_cmd {
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void *cmd;
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enum emac_post_type post_type;
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};
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struct emac_tx_cmd {
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uint8_t *buf;
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uint16_t size;
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int8_t err;
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};
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struct emac_open_cmd {
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int8_t err;
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};
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struct emac_close_cmd {
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int8_t err;
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};
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#define DMA_RX_BUF_NUM CONFIG_DMA_RX_BUF_NUM
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#define DMA_TX_BUF_NUM CONFIG_DMA_TX_BUF_NUM
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#define EMAC_TASK_PRIORITY CONFIG_EMAC_TASK_PRIORITY
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#define EMAC_TASK_STACK_SIZE CONFIG_EMAC_TASK_STACK_SIZE
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#define DMA_RX_BUF_SIZE 1600
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#define DMA_TX_BUF_SIZE 1600
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#define FLOW_CONTROL_HIGH_WATERMARK 3
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#define FLOW_CONTROL_LOW_WATERMARK 6
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#define PHY_LINK_CHECK_NUM 5
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#define EMAC_CMD_OK 0
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#define EMAC_CMD_FAIL -1
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#ifdef __cplusplus
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}
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#endif
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#endif
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