529 lines
18 KiB
C
529 lines
18 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include "freertos/xtensa_context.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_spi_flash.h"
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#include "esp_private/panic_reason.h"
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#include "esp_private/system_internal.h"
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#include "esp_debug_helpers.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/cpu.h"
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#include "soc/soc_caps.h"
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#include "soc/rtc.h"
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#include "hal/soc_hal.h"
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#include "hal/cpu_hal.h"
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#include "hal/timer_hal.h"
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#include "sdkconfig.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/cache_err_int.h"
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#include "esp32/dport_access.h"
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#include "esp32/rom/uart.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/cache_err_int.h"
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#include "esp32s2/rom/uart.h"
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#include "soc/extmem_reg.h"
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#include "soc/cache_memory.h"
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#include "soc/rtc_cntl_reg.h"
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#endif
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#include "panic_internal.h"
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extern void esp_panic_handler(panic_info_t*);
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static XtExcFrame* xt_exc_frames[SOC_CPU_CORES_NUM] = {NULL};
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/*
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Panic handlers; these get called when an unhandled exception occurs or the assembly-level
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task switching / interrupt code runs into an unrecoverable error. The default task stack
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overflow handler and abort handler are also in here.
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*/
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/*
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Note: The linker script will put everything in this file in IRAM/DRAM, so it also works with flash cache disabled.
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*/
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static void print_illegal_instruction_details(const void* f)
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{
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XtExcFrame* frame = (XtExcFrame*) f;
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/* Print out memory around the instruction word */
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uint32_t epc = frame->pc;
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epc = (epc & ~0x3) - 4;
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/* check that the address was sane */
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if (epc < SOC_IROM_MASK_LOW || epc >= SOC_IROM_HIGH) {
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return;
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}
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volatile uint32_t* pepc = (uint32_t*)epc;
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panic_print_str("Memory dump at 0x");
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panic_print_hex(epc);
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panic_print_str(": ");
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panic_print_hex(*pepc);
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panic_print_str(" ");
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panic_print_hex(*(pepc + 1));
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panic_print_str(" ");
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panic_print_hex(*(pepc + 2));
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}
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static void print_debug_exception_details(const void* f)
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{
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int debug_rsn;
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asm("rsr.debugcause %0":"=r"(debug_rsn));
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panic_print_str("Debug exception reason: ");
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if (debug_rsn & XCHAL_DEBUGCAUSE_ICOUNT_MASK) {
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panic_print_str("SingleStep ");
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_IBREAK_MASK) {
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panic_print_str("HwBreakpoint ");
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_DBREAK_MASK) {
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//Unlike what the ISA manual says, this core seemingly distinguishes from a DBREAK
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//reason caused by watchdog 0 and one caused by watchdog 1 by setting bit 8 of the
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//debugcause if the cause is watchpoint 1 and clearing it if it's watchpoint 0.
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if (debug_rsn & (1 << 8)) {
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#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
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int core = 0;
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#if !CONFIG_FREERTOS_UNICORE
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if (f == xt_exc_frames[1]) {
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core = 1;
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}
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#endif
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const char *name = pcTaskGetTaskName(xTaskGetCurrentTaskHandleForCPU(core));
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panic_print_str("Stack canary watchpoint triggered (");
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panic_print_str(name);
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panic_print_str(") ");
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#else
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panic_print_str("Watchpoint 1 triggered ");
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#endif
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} else {
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panic_print_str("Watchpoint 0 triggered ");
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}
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_BREAK_MASK) {
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panic_print_str("BREAK instr ");
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_BREAKN_MASK) {
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panic_print_str("BREAKN instr ");
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}
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if (debug_rsn & XCHAL_DEBUGCAUSE_DEBUGINT_MASK) {
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panic_print_str("DebugIntr ");
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}
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}
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static void print_backtrace_entry(uint32_t pc, uint32_t sp)
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{
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panic_print_str("0x");
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panic_print_hex(pc);
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panic_print_str(":0x");
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panic_print_hex(sp);
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}
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static void print_backtrace(const void* f, int core)
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{
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XtExcFrame *frame = (XtExcFrame*) f;
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int depth = 100;
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//Initialize stk_frame with first frame of stack
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esp_backtrace_frame_t stk_frame = {.pc = frame->pc, .sp = frame->a1, .next_pc = frame->a0};
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panic_print_str("\r\nBacktrace: ");
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print_backtrace_entry(esp_cpu_process_stack_pc(stk_frame.pc), stk_frame.sp);
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//Check if first frame is valid
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bool corrupted = !(esp_stack_ptr_is_sane(stk_frame.sp) &&
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esp_ptr_executable((void*)esp_cpu_process_stack_pc(stk_frame.pc)));
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uint32_t i = ((depth <= 0) ? INT32_MAX : depth) - 1; //Account for stack frame that's already printed
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while (i-- > 0 && stk_frame.next_pc != 0 && !corrupted) {
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if (!esp_backtrace_get_next_frame(&stk_frame)) { //Get next stack frame
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corrupted = true;
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}
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panic_print_str(" ");
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print_backtrace_entry(esp_cpu_process_stack_pc(stk_frame.pc), stk_frame.sp);
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}
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//Print backtrace termination marker
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if (corrupted) {
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panic_print_str(" |<-CORRUPTED");
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} else if (stk_frame.next_pc != 0) { //Backtrace continues
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panic_print_str(" |<-CONTINUES");
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}
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}
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static void print_registers(const void *f, int core)
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{
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XtExcFrame* frame = (XtExcFrame*) f;
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int *regs = (int *)frame;
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int x, y;
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const char *sdesc[] = {
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"PC ", "PS ", "A0 ", "A1 ", "A2 ", "A3 ", "A4 ", "A5 ",
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"A6 ", "A7 ", "A8 ", "A9 ", "A10 ", "A11 ", "A12 ", "A13 ",
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"A14 ", "A15 ", "SAR ", "EXCCAUSE", "EXCVADDR", "LBEG ", "LEND ", "LCOUNT "
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};
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/* only dump registers for 'real' crashes, if crashing via abort()
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the register window is no longer useful.
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*/
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panic_print_str("Core ");
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panic_print_dec(core);
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panic_print_str(" register dump:");
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for (x = 0; x < 24; x += 4) {
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panic_print_str("\r\n");
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for (y = 0; y < 4; y++) {
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if (sdesc[x + y][0] != 0) {
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panic_print_str(sdesc[x + y]);
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panic_print_str(": 0x");
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panic_print_hex(regs[x + y + 1]);
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panic_print_str(" ");
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}
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}
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}
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// If the core which triggers the interrupt watchpoint was in ISR context, dump the epc registers.
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if (xPortInterruptedFromISRContext()
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#if !CONFIG_FREERTOS_UNICORE
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&& ((core == 0 && frame->exccause == PANIC_RSN_INTWDT_CPU0) ||
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(core == 1 && frame->exccause == PANIC_RSN_INTWDT_CPU1))
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#endif //!CONFIG_FREERTOS_UNICORE
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) {
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panic_print_str("\r\n");
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uint32_t __value;
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panic_print_str("Core ");
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panic_print_dec(core);
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panic_print_str(" was running in ISR context:\r\n");
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__asm__("rsr.epc1 %0" : "=a"(__value));
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panic_print_str("EPC1 : 0x");
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panic_print_hex(__value);
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__asm__("rsr.epc2 %0" : "=a"(__value));
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panic_print_str(" EPC2 : 0x");
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panic_print_hex(__value);
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__asm__("rsr.epc3 %0" : "=a"(__value));
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panic_print_str(" EPC3 : 0x");
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panic_print_hex(__value);
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__asm__("rsr.epc4 %0" : "=a"(__value));
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panic_print_str(" EPC4 : 0x");
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panic_print_hex(__value);
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}
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}
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static void print_state(const void* f)
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{
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#if !CONFIG_FREERTOS_UNICORE
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int err_core = f == xt_exc_frames[0] ? 0 : 1;
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#else
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int err_core = 0;
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#endif
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print_registers(f, err_core);
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panic_print_str("\r\n");
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print_backtrace(f, err_core);
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panic_print_str("\r\n");
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#if !CONFIG_FREERTOS_UNICORE
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// If there are other frame info, print them as well
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for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
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// `f` is the frame for the offending core, see note above.
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if (err_core != i && xt_exc_frames[i] != NULL) {
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panic_print_str("\r\n");
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print_registers(xt_exc_frames[i], i);
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panic_print_str("\r\n");
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print_backtrace(xt_exc_frames[i], i);
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}
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}
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#endif
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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static inline void print_cache_err_details(const void* f)
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{
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uint32_t vaddr = 0, size = 0;
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uint32_t status[2];
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status[0] = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
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status[1] = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
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for (int i = 0; i < 32; i++) {
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switch (status[0] & BIT(i)) {
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case EXTMEM_IC_SYNC_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG);
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size = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC1_REG);
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panic_print_str("Icache sync parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_IC_PRELOAD_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG);
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size = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG);
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panic_print_str("Icache preload parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_ICACHE_REJECT_ST:
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vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG);
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panic_print_str("Icache reject error occurred while accessing the address 0x");
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panic_print_hex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
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panic_print_str(" (invalid mmu entry)");
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}
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panic_print_str("\r\n");
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break;
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default:
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break;
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}
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switch (status[1] & BIT(i)) {
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case EXTMEM_DC_SYNC_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG);
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size = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC1_REG);
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panic_print_str("Dcache sync parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_DC_PRELOAD_SIZE_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG);
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size = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG);
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panic_print_str("Dcache preload parameter configuration error, the error address and size is 0x");
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panic_print_hex(vaddr);
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panic_print_str("(0x");
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panic_print_hex(size);
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panic_print_str(")\r\n");
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break;
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case EXTMEM_DCACHE_WRITE_FLASH_ST:
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panic_print_str("Write back error occurred while dcache tries to write back to flash\r\n");
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break;
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case EXTMEM_DCACHE_REJECT_ST:
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vaddr = REG_READ(EXTMEM_PRO_DCACHE_REJECT_VADDR_REG);
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panic_print_str("Dcache reject error occurred while accessing the address 0x");
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panic_print_hex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
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panic_print_str(" (invalid mmu entry)");
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}
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panic_print_str("\r\n");
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break;
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case EXTMEM_MMU_ENTRY_FAULT_ST:
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vaddr = REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG);
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panic_print_str("MMU entry fault error occurred while accessing the address 0x");
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panic_print_hex(vaddr);
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if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
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panic_print_str(" (invalid mmu entry)");
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}
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panic_print_str("\r\n");
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break;
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default:
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break;
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}
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}
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}
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#endif
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static void frame_to_panic_info(XtExcFrame *frame, panic_info_t* info, bool pseudo_excause)
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{
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info->core = cpu_hal_get_core_id();
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info->exception = PANIC_EXCEPTION_FAULT;
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info->details = NULL;
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if (pseudo_excause) {
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if (frame->exccause == PANIC_RSN_INTWDT_CPU0) {
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info->core = 0;
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info->exception = PANIC_EXCEPTION_IWDT;
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} else if (frame->exccause == PANIC_RSN_INTWDT_CPU1) {
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info->core = 1;
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info->exception = PANIC_EXCEPTION_IWDT;
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} else if (frame->exccause == PANIC_RSN_CACHEERR) {
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info->core = esp_cache_err_get_cpuid();
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} else {}
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//Please keep in sync with PANIC_RSN_* defines
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static const char *pseudo_reason[] = {
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"Unknown reason",
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"Unhandled debug exception",
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"Double exception",
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"Unhandled kernel exception",
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"Coprocessor exception",
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"Interrupt wdt timeout on CPU0",
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"Interrupt wdt timeout on CPU1",
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#if CONFIG_IDF_TARGET_ESP32
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"Cache disabled but cached memory region accessed",
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#elif CONFIG_IDF_TARGET_ESP32S2
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"Cache exception",
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#endif
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};
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info->reason = pseudo_reason[0];
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info->description = NULL;
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if (frame->exccause <= PANIC_RSN_MAX) {
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info->reason = pseudo_reason[frame->exccause];
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}
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if (frame->exccause == PANIC_RSN_DEBUGEXCEPTION) {
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info->details = print_debug_exception_details;
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info->exception = PANIC_EXCEPTION_DEBUG;
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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if(frame->exccause == PANIC_RSN_CACHEERR) {
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info->details = print_cache_err_details;
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}
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#endif
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} else {
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static const char *reason[] = {
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"IllegalInstruction", "Syscall", "InstructionFetchError", "LoadStoreError",
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"Level1Interrupt", "Alloca", "IntegerDivideByZero", "PCValue",
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"Privileged", "LoadStoreAlignment", "res", "res",
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"InstrPDAddrError", "LoadStorePIFDataError", "InstrPIFAddrError", "LoadStorePIFAddrError",
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"InstTLBMiss", "InstTLBMultiHit", "InstFetchPrivilege", "res",
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"InstrFetchProhibited", "res", "res", "res",
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"LoadStoreTLBMiss", "LoadStoreTLBMultihit", "LoadStorePrivilege", "res",
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"LoadProhibited", "StoreProhibited", "res", "res",
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"Cp0Dis", "Cp1Dis", "Cp2Dis", "Cp3Dis",
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"Cp4Dis", "Cp5Dis", "Cp6Dis", "Cp7Dis"
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};
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if (frame->exccause < (sizeof(reason) / sizeof(char *))) {
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info->reason = (reason[frame->exccause]);
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} else {
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info->reason = "Unknown";
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}
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info->description = "Exception was unhandled.";
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if (info->reason == reason[0]) {
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info->details = print_illegal_instruction_details;
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}
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}
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info->state = print_state;
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info->addr = ((void*) ((XtExcFrame*) frame)->pc);
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info->frame = frame;
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}
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static void panic_handler(XtExcFrame *frame, bool pseudo_excause)
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{
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/*
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* Setup environment and perform necessary architecture/chip specific
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* steps here prior to the system panic handler.
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* */
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int core_id = cpu_hal_get_core_id();
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// If multiple cores arrive at panic handler, save frames for all of them
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xt_exc_frames[core_id] = frame;
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#if !CONFIG_FREERTOS_UNICORE
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// These are cases where both CPUs both go into panic handler. The following code ensures
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// only one core proceeds to the system panic handler.
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if (pseudo_excause) {
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#define BUSY_WAIT_IF_TRUE(b) { if (b) while(1); }
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// For WDT expiry, pause the non-offending core - offending core handles panic
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BUSY_WAIT_IF_TRUE(frame->exccause == PANIC_RSN_INTWDT_CPU0 && core_id == 1);
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BUSY_WAIT_IF_TRUE(frame->exccause == PANIC_RSN_INTWDT_CPU1 && core_id == 0);
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// For cache error, pause the non-offending core - offending core handles panic
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BUSY_WAIT_IF_TRUE(frame->exccause == PANIC_RSN_CACHEERR && core_id != esp_cache_err_get_cpuid());
|
|
}
|
|
|
|
ets_delay_us(1);
|
|
SOC_HAL_STALL_OTHER_CORES();
|
|
#endif
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
esp_dport_access_int_abort();
|
|
#endif
|
|
|
|
#if !CONFIG_ESP_PANIC_HANDLER_IRAM
|
|
// Re-enable CPU cache for current CPU if it was disabled
|
|
if (!spi_flash_cache_enabled()) {
|
|
spi_flash_enable_cache(core_id);
|
|
panic_print_str("Re-enable cpu cache.\r\n");
|
|
}
|
|
#endif
|
|
|
|
if (esp_cpu_in_ocd_debug_mode()) {
|
|
if (frame->exccause == PANIC_RSN_INTWDT_CPU0 ||
|
|
frame->exccause == PANIC_RSN_INTWDT_CPU1) {
|
|
timer_ll_wdt_clear_intr_status(&TIMERG1);
|
|
}
|
|
}
|
|
|
|
// Convert architecture exception frame into abstracted panic info
|
|
panic_info_t info;
|
|
frame_to_panic_info(frame, &info, pseudo_excause);
|
|
|
|
// Call the system panic handler
|
|
esp_panic_handler(&info);
|
|
}
|
|
|
|
void panicHandler(XtExcFrame *frame)
|
|
{
|
|
// This panic handler gets called for when the double exception vector,
|
|
// kernel exception vector gets used; as well as handling interrupt-based
|
|
// faults cache error, wdt expiry. EXCAUSE register gets written with
|
|
// one of PANIC_RSN_* values.
|
|
panic_handler(frame, true);
|
|
}
|
|
|
|
void xt_unhandled_exception(XtExcFrame *frame)
|
|
{
|
|
panic_handler(frame, false);
|
|
}
|
|
|
|
static __attribute__((noreturn)) void esp_digital_reset(void)
|
|
{
|
|
// make sure all the panic handler output is sent from UART FIFO
|
|
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
|
|
// switch to XTAL (otherwise we will keep running from the PLL)
|
|
|
|
rtc_clk_cpu_freq_set_xtal();
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
esp_cpu_unstall(PRO_CPU_NUM);
|
|
#endif
|
|
// reset the digital part
|
|
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
|
|
while (true) {
|
|
;
|
|
}
|
|
}
|
|
|
|
void __attribute__((noreturn)) panic_restart(void)
|
|
{
|
|
// If resetting because of a cache error, reset the digital part
|
|
if (esp_cache_err_get_cpuid() != -1) {
|
|
esp_digital_reset();
|
|
} else {
|
|
esp_restart_noos();
|
|
}
|
|
} |