399 lines
14 KiB
C
399 lines
14 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "sdkconfig.h"
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#include <hal/spi_ll.h>
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#include <hal/spi_slave_hal.h>
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#include <soc/lldesc.h>
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#include "driver/spi_common_internal.h"
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#include "driver/spi_slave.h"
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#include "soc/spi_periph.h"
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "esp_pm.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/xtensa_api.h"
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#include "freertos/task.h"
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#include "soc/soc_memory_layout.h"
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#include "driver/gpio.h"
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#include "esp_heap_caps.h"
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static const char *SPI_TAG = "spi_slave";
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#define SPI_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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}
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#define VALID_HOST(x) (x>SPI_HOST && x<=VSPI_HOST)
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#ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM
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#define SPI_SLAVE_ISR_ATTR IRAM_ATTR
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#else
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#define SPI_SLAVE_ISR_ATTR
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#endif
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#ifdef CONFIG_SPI_SLAVE_IN_IRAM
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#define SPI_SLAVE_ATTR IRAM_ATTR
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#else
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#define SPI_SLAVE_ATTR
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#endif
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typedef struct {
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int id;
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spi_slave_interface_config_t cfg;
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intr_handle_t intr;
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spi_slave_hal_context_t hal;
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spi_slave_transaction_t *cur_trans;
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uint32_t flags;
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int max_transfer_sz;
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QueueHandle_t trans_queue;
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QueueHandle_t ret_queue;
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int dma_chan;
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_handle_t pm_lock;
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#endif
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} spi_slave_t;
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static spi_slave_t *spihost[SOC_SPI_PERIPH_NUM];
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static void IRAM_ATTR spi_intr(void *arg);
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static inline bool bus_is_iomux(spi_slave_t *host)
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{
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return host->flags&SPICOMMON_BUSFLAG_IOMUX_PINS;
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}
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static void freeze_cs(spi_slave_t *host)
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{
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gpio_matrix_in(GPIO_FUNC_IN_HIGH, spi_periph_signal[host->id].spics_in, false);
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}
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// Use this function instead of cs_initial to avoid overwrite the output config
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// This is used in test by internal gpio matrix connections
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static inline void restore_cs(spi_slave_t *host)
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{
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if (bus_is_iomux(host)) {
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gpio_iomux_in(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in);
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} else {
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gpio_matrix_in(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in, false);
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}
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}
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esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, int dma_chan)
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{
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bool spi_chan_claimed, dma_chan_claimed;
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esp_err_t ret = ESP_OK;
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esp_err_t err;
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//We only support HSPI/VSPI, period.
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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#if defined(CONFIG_IDF_TARGET_ESP32)
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SPI_CHECK( dma_chan >= 0 && dma_chan <= 2, "invalid dma channel", ESP_ERR_INVALID_ARG );
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#elif defined(CONFIG_IDF_TARGET_ESP32S2BETA)
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SPI_CHECK( dma_chan == 0 || dma_chan == host, "invalid dma channel", ESP_ERR_INVALID_ARG );
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#endif
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SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
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#ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM
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SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM)==0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG);
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#endif
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spi_chan_claimed=spicommon_periph_claim(host, "spi slave");
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SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE);
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bool use_dma = dma_chan != 0;
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if (use_dma) {
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dma_chan_claimed=spicommon_dma_chan_claim(dma_chan);
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if ( !dma_chan_claimed ) {
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spicommon_periph_free( host );
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SPI_CHECK(dma_chan_claimed, "dma channel already in use", ESP_ERR_INVALID_STATE);
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}
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}
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spihost[host] = malloc(sizeof(spi_slave_t));
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if (spihost[host] == NULL) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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memset(spihost[host], 0, sizeof(spi_slave_t));
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memcpy(&spihost[host]->cfg, slave_config, sizeof(spi_slave_interface_config_t));
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spihost[host]->id = host;
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err = spicommon_bus_initialize_io(host, bus_config, dma_chan, SPICOMMON_BUSFLAG_SLAVE|bus_config->flags, &spihost[host]->flags);
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if (err!=ESP_OK) {
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ret = err;
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goto cleanup;
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}
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spicommon_cs_initialize(host, slave_config->spics_io_num, 0, !bus_is_iomux(spihost[host]));
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// The slave DMA suffers from unexpected transactions. Forbid reading if DMA is enabled by disabling the CS line.
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if (use_dma) freeze_cs(spihost[host]);
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int dma_desc_ct = 0;
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spihost[host]->dma_chan = dma_chan;
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if (use_dma) {
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//See how many dma descriptors we need and allocate them
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dma_desc_ct = (bus_config->max_transfer_sz + SPI_MAX_DMA_LEN - 1) / SPI_MAX_DMA_LEN;
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if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given
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spihost[host]->max_transfer_sz = dma_desc_ct * SPI_MAX_DMA_LEN;
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} else {
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//We're limited to non-DMA transfers: the SPI work registers can hold 64 bytes at most.
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spihost[host]->max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE;
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}
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#ifdef CONFIG_PM_ENABLE
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err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_slave",
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&spihost[host]->pm_lock);
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if (err != ESP_OK) {
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ret = err;
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goto cleanup;
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}
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// Lock APB frequency while SPI slave driver is in use
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esp_pm_lock_acquire(spihost[host]->pm_lock);
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#endif //CONFIG_PM_ENABLE
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//Create queues
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spihost[host]->trans_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *));
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spihost[host]->ret_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *));
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if (!spihost[host]->trans_queue || !spihost[host]->ret_queue) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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int flags = bus_config->intr_flags | ESP_INTR_FLAG_INTRDISABLED;
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err = esp_intr_alloc(spicommon_irqsource_for_host(host), flags, spi_intr, (void *)spihost[host], &spihost[host]->intr);
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if (err != ESP_OK) {
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ret = err;
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goto cleanup;
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}
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spi_slave_hal_context_t *hal = &spihost[host]->hal;
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spi_slave_hal_init(hal, host);
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if (dma_desc_ct) {
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hal->dmadesc_tx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
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hal->dmadesc_rx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
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if (!hal->dmadesc_tx || !hal->dmadesc_rx) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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}
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hal->dmadesc_n = dma_desc_ct;
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hal->rx_lsbfirst = (slave_config->flags & SPI_SLAVE_RXBIT_LSBFIRST) ? 1 : 0;
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hal->tx_lsbfirst = (slave_config->flags & SPI_SLAVE_TXBIT_LSBFIRST) ? 1 : 0;
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hal->mode = slave_config->mode;
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hal->use_dma = use_dma;
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spi_slave_hal_setup_device(hal);
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return ESP_OK;
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cleanup:
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if (spihost[host]) {
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if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue);
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if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue);
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free(spihost[host]->hal.dmadesc_tx);
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free(spihost[host]->hal.dmadesc_rx);
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#ifdef CONFIG_PM_ENABLE
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if (spihost[host]->pm_lock) {
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esp_pm_lock_release(spihost[host]->pm_lock);
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esp_pm_lock_delete(spihost[host]->pm_lock);
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}
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#endif
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}
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spi_slave_hal_deinit(&spihost[host]->hal);
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free(spihost[host]);
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spihost[host] = NULL;
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spicommon_periph_free(host);
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if (dma_chan != 0) spicommon_dma_chan_free(dma_chan);
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return ret;
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}
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esp_err_t spi_slave_free(spi_host_device_t host)
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{
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
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if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue);
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if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue);
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if ( spihost[host]->dma_chan > 0 ) {
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spicommon_dma_chan_free ( spihost[host]->dma_chan );
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}
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free(spihost[host]->hal.dmadesc_tx);
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free(spihost[host]->hal.dmadesc_rx);
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esp_intr_free(spihost[host]->intr);
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_release(spihost[host]->pm_lock);
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esp_pm_lock_delete(spihost[host]->pm_lock);
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#endif //CONFIG_PM_ENABLE
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free(spihost[host]);
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spihost[host] = NULL;
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spicommon_periph_free(host);
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return ESP_OK;
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}
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esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
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{
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BaseType_t r;
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer),
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"txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->rx_buffer==NULL ||
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(esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) &&
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(trans_desc->length%4==0)),
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"rxdata not in DMA-capable memory or not WORD aligned", ESP_ERR_INVALID_ARG);
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SPI_CHECK(trans_desc->length <= spihost[host]->max_transfer_sz * 8, "data transfer > host maximum", ESP_ERR_INVALID_ARG);
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r = xQueueSend(spihost[host]->trans_queue, (void *)&trans_desc, ticks_to_wait);
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if (!r) return ESP_ERR_TIMEOUT;
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esp_intr_enable(spihost[host]->intr);
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return ESP_OK;
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}
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esp_err_t SPI_SLAVE_ATTR spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait)
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{
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BaseType_t r;
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
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r = xQueueReceive(spihost[host]->ret_queue, (void *)trans_desc, ticks_to_wait);
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if (!r) return ESP_ERR_TIMEOUT;
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return ESP_OK;
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}
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esp_err_t SPI_SLAVE_ATTR spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
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{
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esp_err_t ret;
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spi_slave_transaction_t *ret_trans;
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//ToDo: check if any spi transfers in flight
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ret = spi_slave_queue_trans(host, trans_desc, ticks_to_wait);
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if (ret != ESP_OK) return ret;
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ret = spi_slave_get_trans_result(host, &ret_trans, ticks_to_wait);
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if (ret != ESP_OK) return ret;
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assert(ret_trans == trans_desc);
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return ESP_OK;
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}
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#ifdef DEBUG_SLAVE
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static void dumpregs(spi_dev_t *hw)
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{
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ets_printf("***REG DUMP ***\n");
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ets_printf("mosi_dlen : %08X\n", hw->mosi_dlen.val);
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ets_printf("miso_dlen : %08X\n", hw->miso_dlen.val);
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ets_printf("slv_wrbuf_dlen : %08X\n", hw->slv_wrbuf_dlen.val);
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ets_printf("slv_rdbuf_dlen : %08X\n", hw->slv_rdbuf_dlen.val);
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ets_printf("slave : %08X\n", hw->slave.val);
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ets_printf("slv_rdata_bit : %x\n", hw->slv_rd_bit.slv_rdata_bit);
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ets_printf("dma_rx_status : %08X\n", hw->dma_rx_status);
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ets_printf("dma_tx_status : %08X\n", hw->dma_tx_status);
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}
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static void dumpll(lldesc_t *ll)
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{
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ets_printf("****LL DUMP****\n");
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ets_printf("Size %d\n", ll->size);
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ets_printf("Len: %d\n", ll->length);
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ets_printf("Owner: %s\n", ll->owner ? "dma" : "cpu");
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}
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#endif
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static void SPI_SLAVE_ISR_ATTR spi_slave_restart_after_dmareset(void *arg)
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{
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spi_slave_t *host = (spi_slave_t *)arg;
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esp_intr_enable(host->intr);
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}
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//This is run in interrupt context and apart from initialization and destruction, this is the only code
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//touching the host (=spihost[x]) variable. The rest of the data arrives in queues. That is why there are
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//no muxes in this code.
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static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
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{
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BaseType_t r;
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BaseType_t do_yield = pdFALSE;
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spi_slave_transaction_t *trans = NULL;
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spi_slave_t *host = (spi_slave_t *)arg;
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spi_slave_hal_context_t *hal = &host->hal;
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#ifdef DEBUG_SLAVE
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dumpregs(host->hw);
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if (host->dmadesc_rx) dumpll(&host->dmadesc_rx[0]);
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#endif
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assert(spi_slave_hal_usr_is_done(hal));
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bool use_dma = host->dma_chan != 0;
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if (host->cur_trans) {
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// When DMA is enabled, the slave rx dma suffers from unexpected transactions. Forbid reading until transaction ready.
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if (use_dma) freeze_cs(host);
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spi_slave_hal_store_result(hal);
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host->cur_trans->trans_len = spi_slave_hal_get_rcv_bitlen(hal);
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if (spi_slave_hal_dma_need_reset(hal)) {
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spicommon_dmaworkaround_req_reset(host->dma_chan, spi_slave_restart_after_dmareset, host);
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}
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if (host->cfg.post_trans_cb) host->cfg.post_trans_cb(host->cur_trans);
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//Okay, transaction is done.
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//Return transaction descriptor.
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xQueueSendFromISR(host->ret_queue, &host->cur_trans, &do_yield);
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host->cur_trans = NULL;
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}
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if (use_dma) {
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spicommon_dmaworkaround_idle(host->dma_chan);
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if (spicommon_dmaworkaround_reset_in_progress()) {
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//We need to wait for the reset to complete. Disable int (will be re-enabled on reset callback) and exit isr.
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esp_intr_disable(host->intr);
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if (do_yield) portYIELD_FROM_ISR();
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return;
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}
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}
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//Disable interrupt before checking to avoid concurrency issue.
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esp_intr_disable(host->intr);
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//Grab next transaction
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r = xQueueReceiveFromISR(host->trans_queue, &trans, &do_yield);
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if (r) {
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//enable the interrupt again if there is packet to send
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esp_intr_enable(host->intr);
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//We have a transaction. Send it.
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host->cur_trans = trans;
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hal->bitlen = trans->length;
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hal->rx_buffer = trans->rx_buffer;
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hal->tx_buffer = trans->tx_buffer;
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if (use_dma) {
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spicommon_dmaworkaround_transfer_active(host->dma_chan);
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}
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spi_slave_hal_prepare_data(hal);
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//The slave rx dma get disturbed by unexpected transaction. Only connect the CS when slave is ready.
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if (use_dma) {
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restore_cs(host);
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}
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//Kick off transfer
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spi_slave_hal_user_start(hal);
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if (host->cfg.post_setup_cb) host->cfg.post_setup_cb(trans);
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}
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if (do_yield) portYIELD_FROM_ISR();
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}
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