24011ddd05
1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
265 lines
12 KiB
C
265 lines
12 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_IO_MUX_REG_H_
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#define _SOC_IO_MUX_REG_H_
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#include "soc.h"
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#define SLP_OE (BIT(0))
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#define SLP_SEL (BIT(1))
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#define SLP_PD (BIT(2))
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#define SLP_PU (BIT(3))
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#define SLP_IE (BIT(4))
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#define SLP_DRV 0x3
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#define SLP_DRV_S 5
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#define FUN_PD (BIT(7))
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#define FUN_PU (BIT(8))
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#define FUN_IE (BIT(9))
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#define FUN_DRV 0x3
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#define FUN_DRV_S 10
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#define MCU_SEL 0x7
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#define MCU_SEL_S 12
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#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
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#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
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#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
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#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
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#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
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#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
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#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00)
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#define CLK_OUT3 0xf
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#define CLK_OUT3_S 8
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#define CLK_OUT2 0xf
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#define CLK_OUT2_S 4
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#define CLK_OUT1 0xf
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#define CLK_OUT1_S 0
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#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04)
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#define FUNC_GPIO36_GPIO36 2
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#define FUNC_GPIO36_GPIO36_0 0
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#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08)
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#define FUNC_GPIO37_GPIO37 2
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#define FUNC_GPIO37_GPIO37_0 0
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#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c)
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#define FUNC_GPIO38_GPIO38 2
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#define FUNC_GPIO38_GPIO38_0 0
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#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10)
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#define FUNC_GPIO39_GPIO39 2
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#define FUNC_GPIO39_GPIO39_0 0
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#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14)
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#define FUNC_GPIO34_GPIO34 2
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#define FUNC_GPIO34_GPIO34_0 0
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#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18)
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#define FUNC_GPIO35_GPIO35 2
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#define FUNC_GPIO35_GPIO35_0 0
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#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c)
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#define FUNC_GPIO32_GPIO32 2
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#define FUNC_GPIO32_GPIO32_0 0
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#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20)
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#define FUNC_GPIO33_GPIO33 2
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#define FUNC_GPIO33_GPIO33_0 0
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#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24)
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#define FUNC_GPIO25_EMAC_RXD0 5
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#define FUNC_GPIO25_GPIO25 2
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#define FUNC_GPIO25_GPIO25_0 0
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#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28)
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#define FUNC_GPIO26_EMAC_RXD1 5
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#define FUNC_GPIO26_GPIO26 2
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#define FUNC_GPIO26_GPIO26_0 0
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#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c)
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#define FUNC_GPIO27_EMAC_RX_DV 5
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#define FUNC_GPIO27_GPIO27 2
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#define FUNC_GPIO27_GPIO27_0 0
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#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30)
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#define FUNC_MTMS_EMAC_TXD2 5
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#define FUNC_MTMS_SD_CLK 4
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#define FUNC_MTMS_HS2_CLk 3
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#define FUNC_MTMS_GPIO14 2
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#define FUNC_MTMS_HSPICLK 1
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#define FUNC_MTMS_MTMS 0
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#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34)
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#define FUNC_MTDI_EMAC_TXD3 5
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#define FUNC_MTDI_SD_DATA2 4
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#define FUNC_MTDI_HS2_DATA2 3
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#define FUNC_MTDI_GPIO12 2
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#define FUNC_MTDI_HSPIQ 1
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#define FUNC_MTDI_MTDI 0
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#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38)
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#define FUNC_MTCK_EMAC_RX_ER 5
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#define FUNC_MTCK_SD_DATA3 4
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#define FUNC_MTCK_HS2_DATA3 3
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#define FUNC_MTCK_GPIO13 2
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#define FUNC_MTCK_HSPID 1
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#define FUNC_MTCK_MTCK 0
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#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c)
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#define FUNC_MTDO_EMAC_RXD3 5
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#define FUNC_MTDO_SD_CMD 4
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#define FUNC_MTDO_HS2_CMD 3
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#define FUNC_MTDO_GPIO15 2
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#define FUNC_MTDO_HSPICS0 1
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#define FUNC_MTDO_MTDO 0
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#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40)
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#define FUNC_GPIO2_SD_DATA0 4
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#define FUNC_GPIO2_HS2_DATA0 3
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#define FUNC_GPIO2_GPIO2 2
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#define FUNC_GPIO2_HSPIWP 1
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#define FUNC_GPIO2_GPIO2_0 0
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#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44)
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#define FUNC_GPIO0_EMAC_TX_CLK 5
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#define FUNC_GPIO0_GPIO0 2
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#define FUNC_GPIO0_CLK_OUT1 1
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#define FUNC_GPIO0_GPIO0_0 0
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#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48)
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#define FUNC_GPIO4_EMAC_TX_ER 5
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#define FUNC_GPIO4_SD_DATA1 4
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#define FUNC_GPIO4_HS2_DATA1 3
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#define FUNC_GPIO4_GPIO4 2
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#define FUNC_GPIO4_HSPIHD 1
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#define FUNC_GPIO4_GPIO4_0 0
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#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c)
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#define FUNC_GPIO16_EMAC_CLK_OUT 5
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#define FUNC_GPIO16_U2RXD 4
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#define FUNC_GPIO16_HS1_DATA4 3
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#define FUNC_GPIO16_GPIO16 2
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#define FUNC_GPIO16_GPIO16_0 0
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#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50)
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#define FUNC_GPIO17_EMAC_CLK_OUT_180 5
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#define FUNC_GPIO17_U2TXD 4
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#define FUNC_GPIO17_HS1_DATA5 3
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#define FUNC_GPIO17_GPIO17 2
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#define FUNC_GPIO17_GPIO17_0 0
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#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54)
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#define FUNC_SD_DATA2_U1RXD 4
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#define FUNC_SD_DATA2_HS1_DATA2 3
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#define FUNC_SD_DATA2_GPIO9 2
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#define FUNC_SD_DATA2_SPIHD 1
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#define FUNC_SD_DATA2_SD_DATA2 0
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#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58)
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#define FUNC_SD_DATA3_U1TXD 4
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#define FUNC_SD_DATA3_HS1_DATA3 3
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#define FUNC_SD_DATA3_GPIO10 2
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#define FUNC_SD_DATA3_SPIWP 1
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#define FUNC_SD_DATA3_SD_DATA3 0
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#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c)
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#define FUNC_SD_CMD_U1RTS 4
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#define FUNC_SD_CMD_HS1_CMD 3
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#define FUNC_SD_CMD_GPIO11 2
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#define FUNC_SD_CMD_SPICS0 1
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#define FUNC_SD_CMD_SD_CMD 0
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#define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60)
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#define FUNC_SD_CLK_U1CTS 4
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#define FUNC_SD_CLK_HS1_CLK 3
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#define FUNC_SD_CLK_GPIO6 2
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#define FUNC_SD_CLK_SPICLK 1
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#define FUNC_SD_CLK_SD_CLK 0
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#define PERIPHS_IO_MUX_SD_DATA0_U (DR_REG_IO_MUX_BASE +0x64)
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#define FUNC_SD_DATA0_U2RTS 4
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#define FUNC_SD_DATA0_HS1_DATA0 3
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#define FUNC_SD_DATA0_GPIO7 2
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#define FUNC_SD_DATA0_SPIQ 1
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#define FUNC_SD_DATA0_SD_DATA0 0
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#define PERIPHS_IO_MUX_SD_DATA1_U (DR_REG_IO_MUX_BASE +0x68)
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#define FUNC_SD_DATA1_U2CTS 4
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#define FUNC_SD_DATA1_HS1_DATA1 3
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#define FUNC_SD_DATA1_GPIO8 2
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#define FUNC_SD_DATA1_SPID 1
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#define FUNC_SD_DATA1_SD_DATA1 0
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#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c)
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#define FUNC_GPIO5_EMAC_RX_CLK 5
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#define FUNC_GPIO5_HS1_DATA6 3
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#define FUNC_GPIO5_GPIO5 2
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#define FUNC_GPIO5_VSPICS0 1
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#define FUNC_GPIO5_GPIO5_0 0
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#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70)
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#define FUNC_GPIO18_HS1_DATA7 3
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#define FUNC_GPIO18_GPIO18 2
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#define FUNC_GPIO18_VSPICLK 1
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#define FUNC_GPIO18_GPIO18_0 0
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#define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74)
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#define FUNC_GPIO19_EMAC_TXD0 5
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#define FUNC_GPIO19_U0CTS 3
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#define FUNC_GPIO19_GPIO19 2
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#define FUNC_GPIO19_VSPIQ 1
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#define FUNC_GPIO19_GPIO19_0 0
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#define PERIPHS_IO_MUX_GPIO20_U (DR_REG_IO_MUX_BASE +0x78)
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#define FUNC_GPIO20_GPIO20 2
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#define FUNC_GPIO20_GPIO20_0 0
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#define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c)
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#define FUNC_GPIO21_EMAC_TX_EN 5
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#define FUNC_GPIO21_GPIO21 2
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#define FUNC_GPIO21_VSPIHD 1
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#define FUNC_GPIO21_GPIO21_0 0
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#define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80)
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#define FUNC_GPIO22_EMAC_TXD1 5
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#define FUNC_GPIO22_U0RTS 3
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#define FUNC_GPIO22_GPIO22 2
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#define FUNC_GPIO22_VSPIWP 1
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#define FUNC_GPIO22_GPIO22_0 0
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#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84)
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#define FUNC_U0RXD_GPIO3 2
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#define FUNC_U0RXD_CLK_OUT2 1
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#define FUNC_U0RXD_U0RXD 0
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#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88)
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#define FUNC_U0TXD_EMAC_RXD2 3
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#define FUNC_U0TXD_GPIO1 2
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#define FUNC_U0TXD_CLK_OUT3 1
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#define FUNC_U0TXD_U0TXD 0
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#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c)
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#define FUNC_GPIO23_HS1_STROBE 3
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#define FUNC_GPIO23_GPIO23 2
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#define FUNC_GPIO23_VSPID 1
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#define FUNC_GPIO23_GPIO23_0 0
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#define PERIPHS_IO_MUX_GPIO24_U (DR_REG_IO_MUX_BASE +0x90)
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#define FUNC_GPIO24_GPIO24 2
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#define FUNC_GPIO24_GPIO24_0 0
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#endif /* _SOC_IO_MUX_REG_H_ */
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