ad66fbe5ad
The following issues mentioned during MR!341 review were fixed: 1) Core dump test application description 2) Usage of CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH and CONFIG_ESP32_ENABLE_COREDUMP_TO_UART 3) FLASH_GUARD_START macro usage is fixed in flash API 4) Core dump module logging facility 5) cache util functions doc updated 6) interactive delay before print core dump to uart 7) core dump partion support in build system
52 lines
2 KiB
C
52 lines
2 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef ESP_SPI_FLASH_CACHE_UTILS_H
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#define ESP_SPI_FLASH_CACHE_UTILS_H
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/**
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* This header file contains declarations of cache manipulation functions
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* used both in flash_ops.c and flash_mmap.c.
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*
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* These functions are considered internal and are not designed to be called from applications.
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*/
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// Init mutex protecting access to spi_flash_* APIs
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void spi_flash_init_lock();
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// Take mutex protecting access to spi_flash_* APIs
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void spi_flash_op_lock();
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// Release said mutex
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void spi_flash_op_unlock();
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// Suspend the scheduler on both CPUs, disable cache.
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// Contrary to its name this doesn't do anything with interrupts, yet.
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// Interrupt disabling capability will be added once we implement
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// interrupt allocation API.
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void spi_flash_disable_interrupts_caches_and_other_cpu();
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// Enable cache, enable interrupts (to be added in future), resume scheduler
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void spi_flash_enable_interrupts_caches_and_other_cpu();
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// Disables non-IRAM interrupt handlers on current CPU and caches on both CPUs.
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// This function is implied to be called when other CPU is not running or running code from IRAM.
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void spi_flash_disable_interrupts_caches_and_other_cpu_no_os();
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// Enable cache, enable interrupts on current CPU.
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// This function is implied to be called when other CPU is not running or running code from IRAM.
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void spi_flash_enable_interrupts_caches_no_os();
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#endif //ESP_SPI_FLASH_CACHE_UTILS_H
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