The DMA cannot receive data correctly when the buffer address is not WORD aligned. Currently we only check whether the buffer is in the DRAM region. The DMA always write in WORDs, so the length arguments should also be multiples of 32 bits. A check is added to see whether the buffer is WORD aligned and has valid length.
507 lines
20 KiB
C
507 lines
20 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "driver/spi_common.h"
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#include "driver/spi_slave.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_periph.h"
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#include "rom/ets_sys.h"
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_intr.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "esp_pm.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/xtensa_api.h"
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#include "freertos/task.h"
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#include "soc/soc.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/dport_reg.h"
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#include "rom/lldesc.h"
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#include "driver/gpio.h"
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#include "driver/periph_ctrl.h"
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#include "esp_heap_caps.h"
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static const char *SPI_TAG = "spi_slave";
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#define SPI_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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}
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#define VALID_HOST(x) (x>SPI_HOST && x<=VSPI_HOST)
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#ifdef CONFIG_SPI_SLAVE_ISR_IN_IRAM
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#define SPI_SLAVE_ISR_ATTR IRAM_ATTR
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#else
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#define SPI_SLAVE_ISR_ATTR
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#endif
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#ifdef CONFIG_SPI_SLAVE_IN_IRAM
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#define SPI_SLAVE_ATTR IRAM_ATTR
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#else
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#define SPI_SLAVE_ATTR
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#endif
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typedef struct {
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int id;
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spi_slave_interface_config_t cfg;
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intr_handle_t intr;
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spi_dev_t *hw;
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spi_slave_transaction_t *cur_trans;
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lldesc_t *dmadesc_tx;
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lldesc_t *dmadesc_rx;
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uint32_t flags;
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int max_transfer_sz;
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QueueHandle_t trans_queue;
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QueueHandle_t ret_queue;
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int dma_chan;
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_handle_t pm_lock;
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#endif
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} spi_slave_t;
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static spi_slave_t *spihost[3];
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static void IRAM_ATTR spi_intr(void *arg);
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static inline bool bus_is_iomux(spi_slave_t *host)
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{
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return host->flags&SPICOMMON_BUSFLAG_NATIVE_PINS;
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}
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static void freeze_cs(spi_slave_t *host)
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{
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gpio_matrix_in(GPIO_FUNC_IN_HIGH, spi_periph_signal[host->id].spics_in, false);
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}
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// Use this function instead of cs_initial to avoid overwrite the output config
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// This is used in test by internal gpio matrix connections
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static inline void restore_cs(spi_slave_t *host)
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{
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if (bus_is_iomux(host)) {
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gpio_iomux_in(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in);
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} else {
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gpio_matrix_in(host->cfg.spics_io_num, spi_periph_signal[host->id].spics_in, false);
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}
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}
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esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, int dma_chan)
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{
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bool spi_chan_claimed, dma_chan_claimed;
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esp_err_t ret = ESP_OK;
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esp_err_t err;
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//We only support HSPI/VSPI, period.
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK( dma_chan >= 0 && dma_chan <= 2, "invalid dma channel", ESP_ERR_INVALID_ARG );
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SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
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#ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM
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SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM)==0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG);
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#endif
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spi_chan_claimed=spicommon_periph_claim(host, "spi slave");
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SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE);
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if ( dma_chan != 0 ) {
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dma_chan_claimed=spicommon_dma_chan_claim(dma_chan);
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if ( !dma_chan_claimed ) {
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spicommon_periph_free( host );
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SPI_CHECK(dma_chan_claimed, "dma channel already in use", ESP_ERR_INVALID_STATE);
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}
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}
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spihost[host] = malloc(sizeof(spi_slave_t));
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if (spihost[host] == NULL) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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memset(spihost[host], 0, sizeof(spi_slave_t));
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memcpy(&spihost[host]->cfg, slave_config, sizeof(spi_slave_interface_config_t));
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spihost[host]->id = host;
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err = spicommon_bus_initialize_io(host, bus_config, dma_chan, SPICOMMON_BUSFLAG_SLAVE|bus_config->flags, &spihost[host]->flags);
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if (err!=ESP_OK) {
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ret = err;
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goto cleanup;
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}
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spicommon_cs_initialize(host, slave_config->spics_io_num, 0, !bus_is_iomux(spihost[host]));
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// The slave DMA suffers from unexpected transactions. Forbid reading if DMA is enabled by disabling the CS line.
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if (dma_chan != 0) freeze_cs(spihost[host]);
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spihost[host]->dma_chan = dma_chan;
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if (dma_chan != 0) {
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//See how many dma descriptors we need and allocate them
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int dma_desc_ct = (bus_config->max_transfer_sz + SPI_MAX_DMA_LEN - 1) / SPI_MAX_DMA_LEN;
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if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given
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spihost[host]->max_transfer_sz = dma_desc_ct * SPI_MAX_DMA_LEN;
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spihost[host]->dmadesc_tx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
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spihost[host]->dmadesc_rx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
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if (!spihost[host]->dmadesc_tx || !spihost[host]->dmadesc_rx) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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} else {
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//We're limited to non-DMA transfers: the SPI work registers can hold 64 bytes at most.
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spihost[host]->max_transfer_sz = 16 * 4;
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}
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#ifdef CONFIG_PM_ENABLE
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err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_slave",
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&spihost[host]->pm_lock);
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if (err != ESP_OK) {
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ret = err;
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goto cleanup;
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}
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// Lock APB frequency while SPI slave driver is in use
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esp_pm_lock_acquire(spihost[host]->pm_lock);
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#endif //CONFIG_PM_ENABLE
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//Create queues
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spihost[host]->trans_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *));
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spihost[host]->ret_queue = xQueueCreate(slave_config->queue_size, sizeof(spi_slave_transaction_t *));
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if (!spihost[host]->trans_queue || !spihost[host]->ret_queue) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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int flags = bus_config->intr_flags | ESP_INTR_FLAG_INTRDISABLED;
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err = esp_intr_alloc(spicommon_irqsource_for_host(host), flags, spi_intr, (void *)spihost[host], &spihost[host]->intr);
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if (err != ESP_OK) {
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ret = err;
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goto cleanup;
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}
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spihost[host]->hw = spicommon_hw_for_host(host);
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//Configure slave
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spihost[host]->hw->clock.val = 0;
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spihost[host]->hw->user.val = 0;
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spihost[host]->hw->ctrl.val = 0;
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spihost[host]->hw->slave.wr_rd_buf_en = 1; //no sure if needed
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spihost[host]->hw->user.doutdin = 1; //we only support full duplex
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spihost[host]->hw->user.sio = 0;
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spihost[host]->hw->slave.slave_mode = 1;
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spihost[host]->hw->dma_conf.val |= SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST;
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spihost[host]->hw->dma_out_link.start = 0;
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spihost[host]->hw->dma_in_link.start = 0;
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spihost[host]->hw->dma_conf.val &= ~(SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST);
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spihost[host]->hw->dma_conf.out_data_burst_en = 1;
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spihost[host]->hw->slave.sync_reset = 1;
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spihost[host]->hw->slave.sync_reset = 0;
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bool nodelay = true;
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spihost[host]->hw->ctrl.rd_bit_order = (slave_config->flags & SPI_SLAVE_RXBIT_LSBFIRST) ? 1 : 0;
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spihost[host]->hw->ctrl.wr_bit_order = (slave_config->flags & SPI_SLAVE_TXBIT_LSBFIRST) ? 1 : 0;
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if (slave_config->mode == 0) {
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spihost[host]->hw->pin.ck_idle_edge = 0;
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spihost[host]->hw->user.ck_i_edge = 1;
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spihost[host]->hw->ctrl2.miso_delay_mode = nodelay ? 0 : 2;
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} else if (slave_config->mode == 1) {
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spihost[host]->hw->pin.ck_idle_edge = 0;
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spihost[host]->hw->user.ck_i_edge = 0;
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spihost[host]->hw->ctrl2.miso_delay_mode = nodelay ? 0 : 1;
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} else if (slave_config->mode == 2) {
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spihost[host]->hw->pin.ck_idle_edge = 1;
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spihost[host]->hw->user.ck_i_edge = 0;
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spihost[host]->hw->ctrl2.miso_delay_mode = nodelay ? 0 : 1;
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} else if (slave_config->mode == 3) {
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spihost[host]->hw->pin.ck_idle_edge = 1;
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spihost[host]->hw->user.ck_i_edge = 1;
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spihost[host]->hw->ctrl2.miso_delay_mode = nodelay ? 0 : 2;
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}
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//Reset DMA
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spihost[host]->hw->dma_conf.val |= SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST;
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spihost[host]->hw->dma_out_link.start = 0;
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spihost[host]->hw->dma_in_link.start = 0;
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spihost[host]->hw->dma_conf.val &= ~(SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST);
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//Disable unneeded ints
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spihost[host]->hw->slave.rd_buf_done = 0;
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spihost[host]->hw->slave.wr_buf_done = 0;
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spihost[host]->hw->slave.rd_sta_done = 0;
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spihost[host]->hw->slave.wr_sta_done = 0;
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spihost[host]->hw->slave.rd_buf_inten = 0;
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spihost[host]->hw->slave.wr_buf_inten = 0;
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spihost[host]->hw->slave.rd_sta_inten = 0;
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spihost[host]->hw->slave.wr_sta_inten = 0;
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//Force a transaction done interrupt. This interrupt won't fire yet because we initialized the SPI interrupt as
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//disabled. This way, we can just enable the SPI interrupt and the interrupt handler will kick in, handling
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//any transactions that are queued.
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spihost[host]->hw->slave.trans_inten = 1;
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spihost[host]->hw->slave.trans_done = 1;
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return ESP_OK;
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cleanup:
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if (spihost[host]) {
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if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue);
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if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue);
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free(spihost[host]->dmadesc_tx);
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free(spihost[host]->dmadesc_rx);
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#ifdef CONFIG_PM_ENABLE
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if (spihost[host]->pm_lock) {
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esp_pm_lock_release(spihost[host]->pm_lock);
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esp_pm_lock_delete(spihost[host]->pm_lock);
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}
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#endif
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}
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free(spihost[host]);
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spihost[host] = NULL;
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spicommon_periph_free(host);
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spicommon_dma_chan_free(dma_chan);
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return ret;
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}
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esp_err_t spi_slave_free(spi_host_device_t host)
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{
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
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if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue);
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if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue);
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if ( spihost[host]->dma_chan > 0 ) {
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spicommon_dma_chan_free ( spihost[host]->dma_chan );
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}
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free(spihost[host]->dmadesc_tx);
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free(spihost[host]->dmadesc_rx);
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esp_intr_free(spihost[host]->intr);
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_release(spihost[host]->pm_lock);
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esp_pm_lock_delete(spihost[host]->pm_lock);
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#endif //CONFIG_PM_ENABLE
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free(spihost[host]);
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spihost[host] = NULL;
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spicommon_periph_free(host);
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return ESP_OK;
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}
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esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
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{
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BaseType_t r;
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer),
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"txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->rx_buffer==NULL ||
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(esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) &&
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(trans_desc->length%4==0)),
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"rxdata not in DMA-capable memory or not WORD aligned", ESP_ERR_INVALID_ARG);
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SPI_CHECK(trans_desc->length <= spihost[host]->max_transfer_sz * 8, "data transfer > host maximum", ESP_ERR_INVALID_ARG);
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r = xQueueSend(spihost[host]->trans_queue, (void *)&trans_desc, ticks_to_wait);
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if (!r) return ESP_ERR_TIMEOUT;
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esp_intr_enable(spihost[host]->intr);
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return ESP_OK;
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}
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esp_err_t SPI_SLAVE_ATTR spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait)
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{
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BaseType_t r;
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SPI_CHECK(VALID_HOST(host), "invalid host", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
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r = xQueueReceive(spihost[host]->ret_queue, (void *)trans_desc, ticks_to_wait);
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if (!r) return ESP_ERR_TIMEOUT;
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return ESP_OK;
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}
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esp_err_t SPI_SLAVE_ATTR spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait)
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{
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esp_err_t ret;
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spi_slave_transaction_t *ret_trans;
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//ToDo: check if any spi transfers in flight
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ret = spi_slave_queue_trans(host, trans_desc, ticks_to_wait);
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if (ret != ESP_OK) return ret;
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ret = spi_slave_get_trans_result(host, &ret_trans, ticks_to_wait);
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if (ret != ESP_OK) return ret;
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assert(ret_trans == trans_desc);
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return ESP_OK;
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}
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#ifdef DEBUG_SLAVE
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static void dumpregs(spi_dev_t *hw)
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{
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ets_printf("***REG DUMP ***\n");
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ets_printf("mosi_dlen : %08X\n", hw->mosi_dlen.val);
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ets_printf("miso_dlen : %08X\n", hw->miso_dlen.val);
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ets_printf("slv_wrbuf_dlen : %08X\n", hw->slv_wrbuf_dlen.val);
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ets_printf("slv_rdbuf_dlen : %08X\n", hw->slv_rdbuf_dlen.val);
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ets_printf("slave : %08X\n", hw->slave.val);
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ets_printf("slv_rdata_bit : %x\n", hw->slv_rd_bit.slv_rdata_bit);
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ets_printf("dma_rx_status : %08X\n", hw->dma_rx_status);
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ets_printf("dma_tx_status : %08X\n", hw->dma_tx_status);
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}
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static void dumpll(lldesc_t *ll)
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{
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ets_printf("****LL DUMP****\n");
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ets_printf("Size %d\n", ll->size);
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ets_printf("Len: %d\n", ll->length);
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ets_printf("Owner: %s\n", ll->owner ? "dma" : "cpu");
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}
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#endif
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static void SPI_SLAVE_ISR_ATTR spi_slave_restart_after_dmareset(void *arg)
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{
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spi_slave_t *host = (spi_slave_t *)arg;
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esp_intr_enable(host->intr);
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}
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//This is run in interrupt context and apart from initialization and destruction, this is the only code
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//touching the host (=spihost[x]) variable. The rest of the data arrives in queues. That is why there are
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//no muxes in this code.
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static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
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{
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BaseType_t r;
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BaseType_t do_yield = pdFALSE;
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spi_slave_transaction_t *trans = NULL;
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spi_slave_t *host = (spi_slave_t *)arg;
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#ifdef DEBUG_SLAVE
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dumpregs(host->hw);
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if (host->dmadesc_rx) dumpll(&host->dmadesc_rx[0]);
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#endif
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//Ignore all but the trans_done int.
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if (!host->hw->slave.trans_done) return;
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if (host->cur_trans) {
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// When DMA is enabled, the slave rx dma suffers from unexpected transactions. Forbid reading until transaction ready.
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if (host->dma_chan != 0) freeze_cs(host);
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//when data of cur_trans->length are all sent, the slv_rdata_bit
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//will be the length sent-1 (i.e. cur_trans->length-1 ), otherwise
|
|
//the length sent.
|
|
host->cur_trans->trans_len = host->hw->slv_rd_bit.slv_rdata_bit;
|
|
if (host->cur_trans->trans_len == host->cur_trans->length - 1) {
|
|
host->cur_trans->trans_len++;
|
|
}
|
|
|
|
if (host->dma_chan == 0 && host->cur_trans->rx_buffer) {
|
|
//Copy result out
|
|
uint32_t *data = host->cur_trans->rx_buffer;
|
|
for (int x = 0; x < host->cur_trans->trans_len; x += 32) {
|
|
uint32_t word;
|
|
int len = host->cur_trans->trans_len - x;
|
|
if (len > 32) len = 32;
|
|
word = host->hw->data_buf[(x / 32)];
|
|
memcpy(&data[x / 32], &word, (len + 7) / 8);
|
|
}
|
|
} else if (host->dma_chan != 0 && host->cur_trans->rx_buffer) {
|
|
int i;
|
|
//In case CS goes high too soon, the transfer is aborted while the DMA channel still thinks it's going. This
|
|
//leads to issues later on, so in that case we need to reset the channel. The state can be detected because
|
|
//the DMA system doesn't give back the offending descriptor; the owner is still set to DMA.
|
|
for (i = 0; host->dmadesc_rx[i].eof == 0 && host->dmadesc_rx[i].owner == 0; i++) ;
|
|
if (host->dmadesc_rx[i].owner) {
|
|
spicommon_dmaworkaround_req_reset(host->dma_chan, spi_slave_restart_after_dmareset, host);
|
|
}
|
|
}
|
|
if (host->cfg.post_trans_cb) host->cfg.post_trans_cb(host->cur_trans);
|
|
//Okay, transaction is done.
|
|
//Return transaction descriptor.
|
|
xQueueSendFromISR(host->ret_queue, &host->cur_trans, &do_yield);
|
|
host->cur_trans = NULL;
|
|
}
|
|
if (host->dma_chan != 0) {
|
|
spicommon_dmaworkaround_idle(host->dma_chan);
|
|
if (spicommon_dmaworkaround_reset_in_progress()) {
|
|
//We need to wait for the reset to complete. Disable int (will be re-enabled on reset callback) and exit isr.
|
|
esp_intr_disable(host->intr);
|
|
if (do_yield) portYIELD_FROM_ISR();
|
|
return;
|
|
}
|
|
}
|
|
|
|
//Grab next transaction
|
|
r = xQueueReceiveFromISR(host->trans_queue, &trans, &do_yield);
|
|
if (!r) {
|
|
//No packet waiting. Disable interrupt.
|
|
esp_intr_disable(host->intr);
|
|
} else {
|
|
//We have a transaction. Send it.
|
|
host->hw->slave.trans_done = 0; //clear int bit
|
|
host->cur_trans = trans;
|
|
|
|
if (host->dma_chan != 0) {
|
|
spicommon_dmaworkaround_transfer_active(host->dma_chan);
|
|
host->hw->dma_conf.val |= SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST;
|
|
host->hw->dma_out_link.start = 0;
|
|
host->hw->dma_in_link.start = 0;
|
|
host->hw->dma_conf.val &= ~(SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST);
|
|
host->hw->dma_conf.out_data_burst_en = 0;
|
|
host->hw->dma_conf.indscr_burst_en = 0;
|
|
host->hw->dma_conf.outdscr_burst_en = 0;
|
|
|
|
//Fill DMA descriptors
|
|
if (trans->rx_buffer) {
|
|
host->hw->user.usr_miso_highpart = 0;
|
|
spicommon_setup_dma_desc_links(host->dmadesc_rx, ((trans->length + 7) / 8), trans->rx_buffer, true);
|
|
host->hw->dma_in_link.addr = (int)(&host->dmadesc_rx[0]) & 0xFFFFF;
|
|
host->hw->dma_in_link.start = 1;
|
|
}
|
|
|
|
if (trans->tx_buffer) {
|
|
spicommon_setup_dma_desc_links(host->dmadesc_tx, (trans->length + 7) / 8, trans->tx_buffer, false);
|
|
host->hw->user.usr_mosi_highpart = 0;
|
|
host->hw->dma_out_link.addr = (int)(&host->dmadesc_tx[0]) & 0xFFFFF;
|
|
host->hw->dma_out_link.start = 1;
|
|
}
|
|
|
|
host->hw->slave.sync_reset = 1;
|
|
host->hw->slave.sync_reset = 0;
|
|
|
|
} else {
|
|
//No DMA. Turn off SPI and copy data to transmit buffers.
|
|
host->hw->cmd.usr = 0;
|
|
host->hw->slave.sync_reset = 1;
|
|
host->hw->slave.sync_reset = 0;
|
|
|
|
host->hw->user.usr_miso_highpart = 0;
|
|
host->hw->user.usr_mosi_highpart = 0;
|
|
if (trans->tx_buffer) {
|
|
const uint32_t *data = host->cur_trans->tx_buffer;
|
|
for (int x = 0; x < trans->length; x += 32) {
|
|
uint32_t word;
|
|
memcpy(&word, &data[x / 32], 4);
|
|
host->hw->data_buf[(x / 32)] = word;
|
|
}
|
|
}
|
|
}
|
|
|
|
host->hw->slv_rd_bit.slv_rdata_bit = 0;
|
|
host->hw->slv_wrbuf_dlen.bit_len = trans->length - 1;
|
|
host->hw->slv_rdbuf_dlen.bit_len = trans->length - 1;
|
|
host->hw->mosi_dlen.usr_mosi_dbitlen = trans->length - 1;
|
|
host->hw->miso_dlen.usr_miso_dbitlen = trans->length - 1;
|
|
host->hw->user.usr_mosi = (trans->tx_buffer == NULL) ? 0 : 1;
|
|
host->hw->user.usr_miso = (trans->rx_buffer == NULL) ? 0 : 1;
|
|
|
|
//The slave rx dma get disturbed by unexpected transaction. Only connect the CS when slave is ready.
|
|
if (host->dma_chan != 0) restore_cs(host);
|
|
|
|
//Kick off transfer
|
|
host->hw->cmd.usr = 1;
|
|
if (host->cfg.post_setup_cb) host->cfg.post_setup_cb(trans);
|
|
}
|
|
if (do_yield) portYIELD_FROM_ISR();
|
|
}
|
|
|