129 lines
4.3 KiB
ArmAsm
129 lines
4.3 KiB
ArmAsm
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include <xtensa/simcall.h>
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#include "freertos/xtensa_context.h"
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#include "esp_panic.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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/*
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In some situations, the panic handler needs to be invoked even when (low/medium priority) interrupts
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are disabled. In that case, we use a high interrupt to panic anyway. This is the high-level interrupt
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handler for such a situation. We use interrupt level 4 for this.
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*/
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.section .iram1,"ax"
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.global xt_highint4
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.type xt_highint4,@function
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.align 4
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xt_highint4:
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/* On the ESP32, this level is used for panic events that are detected by hardware and should
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also panic when interrupts are disabled. At the moment, these are the interrupt watchdog
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as well as the cache invalid access interrupt. (24 and 25) */
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/* Allocate exception frame and save minimal context. */
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mov a0, sp
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addi sp, sp, -XT_STK_FRMSZ
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s32i a0, sp, XT_STK_A1
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -12 /* for debug backtrace */
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#endif
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rsr a0, PS /* save interruptee's PS */
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s32i a0, sp, XT_STK_PS
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rsr a0, EPC_4 /* save interruptee's PC */
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s32i a0, sp, XT_STK_PC
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#if XCHAL_HAVE_WINDOWED
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s32e a0, sp, -16 /* for debug backtrace */
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#endif
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s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
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s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
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call0 _xt_context_save
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/* Save vaddr into exception frame */
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rsr a0, EXCVADDR
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s32i a0, sp, XT_STK_EXCVADDR
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/* Figure out reason, save into EXCCAUSE reg */
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rsr a0, INTERRUPT
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extui a0, a0, ETS_CACHEERR_INUM, 1 /* get cacheerr int bit */
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beqz a0, 1f
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/* Kill this interrupt; we cannot reset it. */
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rsr a0, INTENABLE
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movi a4, ~(1<<ETS_CACHEERR_INUM)
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and a0, a4, a0
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wsr a0, INTENABLE
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movi a0, PANIC_RSN_CACHEERR
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j 9f
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1:
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#if CONFIG_INT_WDT_CHECK_CPU1
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/* Check if the cause is the app cpu failing to tick.*/
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movi a0, int_wdt_app_cpu_ticked
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l32i a0, a0, 0
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bnez a0, 2f
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/* It is. Modify cause. */
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movi a0,PANIC_RSN_INTWDT_CPU1
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j 9f
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2:
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#endif
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/* Set EXCCAUSE to reflect cause of the wdt int trigger */
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movi a0,PANIC_RSN_INTWDT_CPU0
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9:
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/* Found the reason, now save it. */
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s32i a0, sp, XT_STK_EXCCAUSE
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/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
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rsr a0, EXCSAVE_4 /* save interruptee's a0 */
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s32i a0, sp, XT_STK_A0
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/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
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movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
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wsr a0, PS
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//Call panic handler
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mov a6,sp
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call4 panicHandler
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call0 _xt_context_restore
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l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
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wsr a0, PS
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l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
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wsr a0, EPC_4
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l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
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l32i sp, sp, XT_STK_A1 /* remove exception frame */
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rsync /* ensure PS and EPC written */
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rsr a0, EXCSAVE_4 /* restore a0 */
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rfi 4
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/* The linker has no reason to link in this file; all symbols it exports are already defined
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(weakly!) in the default int handler. Define a symbol here so we can use it to have the
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linker inspect this anyway. */
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.global ld_include_panic_highint_hdl
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ld_include_panic_highint_hdl:
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