OVMS3-idf/components/soc
Ivan Grokhotkov b4939b1121 bootloader, esp32: add workaround for Tensilica erratum 572
If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
2019-01-23 16:23:08 +08:00
..
esp32 bootloader, esp32: add workaround for Tensilica erratum 572 2019-01-23 16:23:08 +08:00
include/soc soc: Fix check_long_hold_gpio and move def to soc 2018-06-26 12:47:55 +05:00
test soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
CMakeLists.txt cmake: make main a component again 2018-09-13 11:13:27 +08:00
component.mk Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00