1517aeda6c
The old code calculated MAX() of two enum values, but CPU frequency enum values are not ordered (2MHz goes after 240MHz). This caused incorrect configuration to be set.
488 lines
16 KiB
C
488 lines
16 KiB
C
// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <stdbool.h>
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#include <string.h>
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#include <sys/param.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_pm.h"
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#include "esp_log.h"
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#include "esp_crosscore_int.h"
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#include "soc/rtc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_timer.h"
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#include "xtensa/core-macros.h"
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#include "pm_impl.h"
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#include "pm_trace.h"
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#include "esp_timer_impl.h"
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#include "esp32/pm.h"
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/* CCOMPARE update timeout, in CPU cycles. Any value above ~600 cycles will work
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* for the purpose of detecting a deadlock.
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*/
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#define CCOMPARE_UPDATE_TIMEOUT 1000000
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#ifdef CONFIG_PM_PROFILING
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#define WITH_PROFILING
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#endif
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static portMUX_TYPE s_switch_lock = portMUX_INITIALIZER_UNLOCKED;
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/* The following state variables are protected using s_switch_lock: */
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/* Current sleep mode; When switching, contains old mode until switch is complete */
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static pm_mode_t s_mode = PM_MODE_CPU_MAX;
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/* True when switch is in progress */
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static volatile bool s_is_switching;
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/* When switch is in progress, this is the mode we are switching into */
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static pm_mode_t s_new_mode = PM_MODE_CPU_MAX;
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/* Number of times each mode was locked */
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static size_t s_mode_lock_counts[PM_MODE_COUNT];
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/* Bit mask of locked modes. BIT(i) is set iff s_mode_lock_counts[i] > 0. */
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static uint32_t s_mode_mask;
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/* Divider and multiplier used to adjust (ccompare - ccount) duration.
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* Only set to non-zero values when switch is in progress.
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*/
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static uint32_t s_ccount_div;
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static uint32_t s_ccount_mul;
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/* Indicates to the ISR hook that CCOMPARE needs to be updated on the given CPU.
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* Used in conjunction with cross-core interrupt to update CCOMPARE on the other CPU.
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*/
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static volatile bool s_need_update_ccompare[portNUM_PROCESSORS];
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/* When no RTOS tasks are active, these locks are released to allow going into
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* a lower power mode. Used by ISR hook and idle hook.
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*/
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static esp_pm_lock_handle_t s_rtos_lock_handle[portNUM_PROCESSORS];
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/* A flag indicating that Idle hook has run on a given CPU;
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* Next interrupt on the same CPU will take s_rtos_lock_handle.
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*/
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static bool s_core_idle[portNUM_PROCESSORS];
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/* g_ticks_us defined in ROM for PRO CPU */
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extern uint32_t g_ticks_per_us_pro;
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/* Lookup table of CPU frequencies to be used in each mode.
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* Initialized by esp_pm_impl_init and modified by esp_pm_configure.
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*/
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rtc_cpu_freq_t s_cpu_freq_by_mode[PM_MODE_COUNT];
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/* Lookup table of CPU ticks per microsecond for each RTC_CPU_FREQ_ value.
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* Essentially the same as returned by rtc_clk_cpu_freq_value(), but without
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* the function call. Not const because XTAL frequency is only known at run time.
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*/
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static uint32_t s_cpu_freq_to_ticks[] = {
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[RTC_CPU_FREQ_XTAL] = 0, /* This is set by esp_pm_impl_init */
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[RTC_CPU_FREQ_80M] = 80,
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[RTC_CPU_FREQ_160M] = 160,
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[RTC_CPU_FREQ_240M] = 240,
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[RTC_CPU_FREQ_2M] = 2
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};
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/* Lookup table of names for each RTC_CPU_FREQ_ value. Used for logging only. */
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static const char* s_freq_names[] __attribute__((unused)) = {
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[RTC_CPU_FREQ_XTAL] = "XTAL",
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[RTC_CPU_FREQ_80M] = "80",
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[RTC_CPU_FREQ_160M] = "160",
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[RTC_CPU_FREQ_240M] = "240",
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[RTC_CPU_FREQ_2M] = "2"
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};
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/* Whether automatic light sleep is enabled. Currently always false */
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static bool s_light_sleep_en = false;
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#ifdef WITH_PROFILING
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/* Time, in microseconds, spent so far in each mode */
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static pm_time_t s_time_in_mode[PM_MODE_COUNT];
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/* Timestamp, in microseconds, when the mode switch last happened */
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static pm_time_t s_last_mode_change_time;
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/* User-readable mode names, used by esp_pm_impl_dump_stats */
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static const char* s_mode_names[] = {
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"SLEEP",
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"APB_MIN",
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"APB_MAX",
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"CPU_MAX"
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};
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#endif // WITH_PROFILING
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static const char* TAG = "pm_esp32";
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static void update_ccompare();
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static void do_switch(pm_mode_t new_mode);
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static void leave_idle();
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static void on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us);
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pm_mode_t esp_pm_impl_get_mode(esp_pm_lock_type_t type, int arg)
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{
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(void) arg;
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if (type == ESP_PM_CPU_FREQ_MAX) {
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return PM_MODE_CPU_MAX;
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} else if (type == ESP_PM_APB_FREQ_MAX) {
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return PM_MODE_APB_MAX;
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} else if (type == ESP_PM_NO_LIGHT_SLEEP) {
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return PM_MODE_APB_MIN;
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} else {
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// unsupported mode
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abort();
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}
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}
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/* rtc_cpu_freq_t enum is not ordered by frequency, so convert to MHz,
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* figure out the maximum value, then convert back to rtc_cpu_freq_t.
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*/
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static rtc_cpu_freq_t max_freq_of(rtc_cpu_freq_t f1, rtc_cpu_freq_t f2)
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{
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int f1_hz = rtc_clk_cpu_freq_value(f1);
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int f2_hz = rtc_clk_cpu_freq_value(f2);
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int f_max_hz = MAX(f1_hz, f2_hz);
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rtc_cpu_freq_t result = RTC_CPU_FREQ_XTAL;
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if (!rtc_clk_cpu_freq_from_mhz(f_max_hz/1000000, &result)) {
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assert(false && "unsupported frequency");
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}
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return result;
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}
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esp_err_t esp_pm_configure(const void* vconfig)
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{
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#ifndef CONFIG_PM_ENABLE
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return ESP_ERR_NOT_SUPPORTED;
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#endif
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const esp_pm_config_esp32_t* config = (const esp_pm_config_esp32_t*) vconfig;
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if (config->light_sleep_enable) {
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return ESP_ERR_NOT_SUPPORTED;
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}
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rtc_cpu_freq_t min_freq = config->min_cpu_freq;
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rtc_cpu_freq_t max_freq = config->max_cpu_freq;
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int min_freq_mhz = rtc_clk_cpu_freq_value(min_freq);
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int max_freq_mhz = rtc_clk_cpu_freq_value(max_freq);
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if (min_freq_mhz > max_freq_mhz) {
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return ESP_ERR_INVALID_ARG;
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}
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rtc_cpu_freq_t apb_max_freq; /* CPU frequency in APB_MAX mode */
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if (max_freq == RTC_CPU_FREQ_240M) {
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/* We can't switch between 240 and 80/160 without disabling PLL,
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* so use 240MHz CPU frequency when 80MHz APB frequency is requested.
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*/
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apb_max_freq = RTC_CPU_FREQ_240M;
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} else {
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/* Otherwise (max CPU frequency is 80MHz or 160MHz), can use 80MHz
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* CPU frequency when 80MHz APB frequency is requested.
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*/
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apb_max_freq = RTC_CPU_FREQ_80M;
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}
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apb_max_freq = max_freq_of(apb_max_freq, min_freq);
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ESP_LOGI(TAG, "Frequency switching config: "
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"CPU_MAX: %s, APB_MAX: %s, APB_MIN: %s, Light sleep: %s",
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s_freq_names[max_freq],
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s_freq_names[apb_max_freq],
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s_freq_names[min_freq],
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config->light_sleep_enable ? "ENABLED" : "DISABLED");
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portENTER_CRITICAL(&s_switch_lock);
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s_cpu_freq_by_mode[PM_MODE_CPU_MAX] = max_freq;
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s_cpu_freq_by_mode[PM_MODE_APB_MAX] = apb_max_freq;
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s_cpu_freq_by_mode[PM_MODE_APB_MIN] = min_freq;
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s_cpu_freq_by_mode[PM_MODE_LIGHT_SLEEP] = min_freq;
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s_light_sleep_en = config->light_sleep_enable;
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portEXIT_CRITICAL(&s_switch_lock);
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return ESP_OK;
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}
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static pm_mode_t IRAM_ATTR get_lowest_allowed_mode()
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{
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/* TODO: optimize using ffs/clz */
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if (s_mode_mask >= BIT(PM_MODE_CPU_MAX)) {
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return PM_MODE_CPU_MAX;
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} else if (s_mode_mask >= BIT(PM_MODE_APB_MAX)) {
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return PM_MODE_APB_MAX;
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} else if (s_mode_mask >= BIT(PM_MODE_APB_MIN) || !s_light_sleep_en) {
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return PM_MODE_APB_MIN;
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} else {
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return PM_MODE_LIGHT_SLEEP;
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}
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}
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void IRAM_ATTR esp_pm_impl_switch_mode(pm_mode_t mode,
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pm_mode_switch_t lock_or_unlock, pm_time_t now)
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{
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bool need_switch = false;
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uint32_t mode_mask = BIT(mode);
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portENTER_CRITICAL(&s_switch_lock);
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uint32_t count;
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if (lock_or_unlock == MODE_LOCK) {
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count = ++s_mode_lock_counts[mode];
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} else {
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count = s_mode_lock_counts[mode]--;
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}
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if (count == 1) {
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if (lock_or_unlock == MODE_LOCK) {
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s_mode_mask |= mode_mask;
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} else {
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s_mode_mask &= ~mode_mask;
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}
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need_switch = true;
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}
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pm_mode_t new_mode = s_mode;
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if (need_switch) {
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new_mode = get_lowest_allowed_mode();
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#ifdef WITH_PROFILING
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if (s_last_mode_change_time != 0) {
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pm_time_t diff = now - s_last_mode_change_time;
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s_time_in_mode[s_mode] += diff;
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}
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s_last_mode_change_time = now;
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#endif // WITH_PROFILING
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}
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portEXIT_CRITICAL(&s_switch_lock);
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if (need_switch && new_mode != s_mode) {
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do_switch(new_mode);
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}
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}
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/**
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* @brief Update clock dividers in esp_timer and FreeRTOS, and adjust CCOMPARE
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* values on both CPUs.
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* @param old_ticks_per_us old CPU frequency
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* @param ticks_per_us new CPU frequency
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*/
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static void IRAM_ATTR on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us)
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{
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uint32_t old_apb_ticks_per_us = MIN(old_ticks_per_us, 80);
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uint32_t apb_ticks_per_us = MIN(ticks_per_us, 80);
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/* Update APB frequency value used by the timer */
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if (old_apb_ticks_per_us != apb_ticks_per_us) {
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esp_timer_impl_update_apb_freq(apb_ticks_per_us);
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}
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/* Calculate new tick divisor */
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_xt_tick_divisor = ticks_per_us * 1000000 / XT_TICK_PER_SEC;
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int core_id = xPortGetCoreID();
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if (s_rtos_lock_handle[core_id] != NULL) {
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ESP_PM_TRACE_ENTER(CCOMPARE_UPDATE, core_id);
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/* ccount_div and ccount_mul are used in esp_pm_impl_update_ccompare
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* to calculate new CCOMPARE value.
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*/
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s_ccount_div = old_ticks_per_us;
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s_ccount_mul = ticks_per_us;
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/* Update CCOMPARE value on this CPU */
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update_ccompare();
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#if portNUM_PROCESSORS == 2
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/* Send interrupt to the other CPU to update CCOMPARE value */
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int other_core_id = (core_id == 0) ? 1 : 0;
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s_need_update_ccompare[other_core_id] = true;
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esp_crosscore_int_send_freq_switch(other_core_id);
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int timeout = 0;
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while (s_need_update_ccompare[other_core_id]) {
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if (++timeout == CCOMPARE_UPDATE_TIMEOUT) {
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assert(false && "failed to update CCOMPARE, possible deadlock");
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}
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}
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#endif // portNUM_PROCESSORS == 2
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s_ccount_mul = 0;
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s_ccount_div = 0;
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ESP_PM_TRACE_EXIT(CCOMPARE_UPDATE, core_id);
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}
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}
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/**
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* Perform the switch to new power mode.
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* Currently only changes the CPU frequency and adjusts clock dividers.
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* No light sleep yet.
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* @param new_mode mode to switch to
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*/
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static void IRAM_ATTR do_switch(pm_mode_t new_mode)
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{
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const int core_id = xPortGetCoreID();
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do {
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portENTER_CRITICAL_ISR(&s_switch_lock);
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if (!s_is_switching) {
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break;
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}
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if (s_new_mode <= new_mode) {
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portEXIT_CRITICAL_ISR(&s_switch_lock);
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return;
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}
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if (s_need_update_ccompare[core_id]) {
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s_need_update_ccompare[core_id] = false;
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}
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portEXIT_CRITICAL_ISR(&s_switch_lock);
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} while (true);
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s_new_mode = new_mode;
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s_is_switching = true;
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portEXIT_CRITICAL_ISR(&s_switch_lock);
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rtc_cpu_freq_t old_freq = s_cpu_freq_by_mode[s_mode];
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rtc_cpu_freq_t new_freq = s_cpu_freq_by_mode[new_mode];
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if (new_freq != old_freq) {
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uint32_t old_ticks_per_us = g_ticks_per_us_pro;
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uint32_t new_ticks_per_us = s_cpu_freq_to_ticks[new_freq];
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bool switch_down = new_ticks_per_us < old_ticks_per_us;
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ESP_PM_TRACE_ENTER(FREQ_SWITCH, core_id);
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if (switch_down) {
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on_freq_update(old_ticks_per_us, new_ticks_per_us);
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}
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rtc_clk_cpu_freq_set_fast(new_freq);
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if (!switch_down) {
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on_freq_update(old_ticks_per_us, new_ticks_per_us);
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}
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ESP_PM_TRACE_EXIT(FREQ_SWITCH, core_id);
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}
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portENTER_CRITICAL_ISR(&s_switch_lock);
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s_mode = new_mode;
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s_is_switching = false;
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portEXIT_CRITICAL_ISR(&s_switch_lock);
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}
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/**
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* @brief Calculate new CCOMPARE value based on s_ccount_{mul,div}
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*
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* Adjusts CCOMPARE value so that the interrupt happens at the same time as it
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* would happen without the frequency change.
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* Assumes that the new_frequency = old_frequency * s_ccount_mul / s_ccount_div.
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*/
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static void IRAM_ATTR update_ccompare()
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{
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const uint32_t ccompare_min_cycles_in_future = 1000;
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uint32_t ccount = XTHAL_GET_CCOUNT();
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uint32_t ccompare = XTHAL_GET_CCOMPARE(XT_TIMER_INDEX);
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if ((ccompare - ccompare_min_cycles_in_future) - ccount < UINT32_MAX / 2) {
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uint32_t diff = ccompare - ccount;
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uint32_t diff_scaled = (diff * s_ccount_mul + s_ccount_div - 1) / s_ccount_div;
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if (diff_scaled < _xt_tick_divisor) {
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uint32_t new_ccompare = ccount + diff_scaled;
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XTHAL_SET_CCOMPARE(XT_TIMER_INDEX, new_ccompare);
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}
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}
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}
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static void IRAM_ATTR leave_idle()
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{
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int core_id = xPortGetCoreID();
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if (s_core_idle[core_id]) {
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// TODO: possible optimization: raise frequency here first
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esp_pm_lock_acquire(s_rtos_lock_handle[core_id]);
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s_core_idle[core_id] = false;
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}
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}
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void esp_pm_impl_idle_hook()
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{
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int core_id = xPortGetCoreID();
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uint32_t state = portENTER_CRITICAL_NESTED();
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if (!s_core_idle[core_id]) {
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esp_pm_lock_release(s_rtos_lock_handle[core_id]);
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s_core_idle[core_id] = true;
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}
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portEXIT_CRITICAL_NESTED(state);
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ESP_PM_TRACE_ENTER(IDLE, core_id);
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}
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void IRAM_ATTR esp_pm_impl_isr_hook()
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{
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int core_id = xPortGetCoreID();
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ESP_PM_TRACE_ENTER(ISR_HOOK, core_id);
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#if portNUM_PROCESSORS == 2
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if (s_need_update_ccompare[core_id]) {
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update_ccompare();
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s_need_update_ccompare[core_id] = false;
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} else {
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leave_idle();
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}
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#else
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leave_idle();
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#endif // portNUM_PROCESSORS == 2
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ESP_PM_TRACE_EXIT(ISR_HOOK, core_id);
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}
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#ifdef WITH_PROFILING
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void esp_pm_impl_dump_stats(FILE* out)
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{
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pm_time_t time_in_mode[PM_MODE_COUNT];
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portENTER_CRITICAL_ISR(&s_switch_lock);
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memcpy(time_in_mode, s_time_in_mode, sizeof(time_in_mode));
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pm_time_t last_mode_change_time = s_last_mode_change_time;
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pm_mode_t cur_mode = s_mode;
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pm_time_t now = pm_get_time();
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portEXIT_CRITICAL_ISR(&s_switch_lock);
|
|
|
|
time_in_mode[cur_mode] += now - last_mode_change_time;
|
|
|
|
fprintf(out, "Mode stats:\n");
|
|
for (int i = 0; i < PM_MODE_COUNT; ++i) {
|
|
if (i == PM_MODE_LIGHT_SLEEP && !s_light_sleep_en) {
|
|
/* don't display light sleep mode if it's not enabled */
|
|
continue;
|
|
}
|
|
fprintf(out, "%8s %6s %12lld %2d%%\n",
|
|
s_mode_names[i],
|
|
s_freq_names[s_cpu_freq_by_mode[i]],
|
|
time_in_mode[i],
|
|
(int) (time_in_mode[i] * 100 / now));
|
|
}
|
|
}
|
|
#endif // WITH_PROFILING
|
|
|
|
void esp_pm_impl_init()
|
|
{
|
|
s_cpu_freq_to_ticks[RTC_CPU_FREQ_XTAL] = rtc_clk_xtal_freq_get();
|
|
#ifdef CONFIG_PM_TRACE
|
|
esp_pm_trace_init();
|
|
#endif
|
|
ESP_ERROR_CHECK(esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "rtos0",
|
|
&s_rtos_lock_handle[0]));
|
|
ESP_ERROR_CHECK(esp_pm_lock_acquire(s_rtos_lock_handle[0]));
|
|
#if portNUM_PROCESSORS == 2
|
|
ESP_ERROR_CHECK(esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "rtos1",
|
|
&s_rtos_lock_handle[1]));
|
|
ESP_ERROR_CHECK(esp_pm_lock_acquire(s_rtos_lock_handle[1]));
|
|
|
|
/* Configure all modes to use the default CPU frequency.
|
|
* This will be modified later by a call to esp_pm_configure.
|
|
*/
|
|
rtc_cpu_freq_t default_freq;
|
|
assert(rtc_clk_cpu_freq_from_mhz(CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ, &default_freq));
|
|
for (size_t i = 0; i < PM_MODE_COUNT; ++i) {
|
|
s_cpu_freq_by_mode[i] = default_freq;
|
|
}
|
|
#endif // portNUM_PROCESSORS == 2
|
|
}
|