b6d7675e60
1. Original register mapping for LAN8720 has some registers that doesn't exist/support. So just remove them, and fix the power and init function for LAN8720. 2. GPIO16 and GPIO17 is occupied by PSRAM, so only ETH_CLOCK_GPIO_IN mode is supported in that case if using PSRAM. 3. Fix bug of OTA failing with Ethernet 4. Fix bug of multicast with Ethernet Closes https://github.com/espressif/esp-idf/issues/2564 Closes https://github.com/espressif/esp-idf/issues/2620 Closes https://github.com/espressif/esp-idf/issues/2657
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include <string.h>
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#include "rom/ets_sys.h"
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#include "rom/gpio.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/gpio_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/emac_reg_v2.h"
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#include "soc/emac_ex_reg.h"
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#include "esp_log.h"
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#include "driver/gpio.h"
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#include "sdkconfig.h"
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#include "emac_common.h"
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void emac_enable_flowctrl(void)
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{
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REG_SET_BIT(EMAC_GMACFC_REG, EMAC_TFCE);
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REG_SET_BIT(EMAC_GMACFC_REG, EMAC_RFCE);
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REG_CLR_BIT(EMAC_GMACFC_REG, EMAC_DZPQ);
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REG_SET_FIELD(EMAC_GMACFC_REG, EMAC_PAUSE_TIME, 0x1648);
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REG_SET_FIELD(EMAC_GMACFC_REG, EMAC_PLT, 0x1);
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}
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void emac_disable_flowctrl(void)
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{
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REG_CLR_BIT(EMAC_GMACFC_REG, EMAC_TFCE);
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REG_CLR_BIT(EMAC_GMACFC_REG, EMAC_RFCE);
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REG_CLR_BIT(EMAC_GMACFC_REG, EMAC_DZPQ);
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REG_SET_FIELD(EMAC_GMACFC_REG, EMAC_PAUSE_TIME, 0);
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REG_SET_FIELD(EMAC_GMACFC_REG, EMAC_PLT, 0);
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}
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void emac_enable_dma_tx(void)
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{
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_TRANSMISSION_COMMAND);
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}
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void emac_enable_dma_rx(void)
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{
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_RX);
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}
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void emac_disable_dma_tx(void)
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{
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REG_CLR_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_TRANSMISSION_COMMAND);
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}
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void emac_disable_dma_rx(void)
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{
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REG_CLR_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_RX);
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}
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void emac_enable_clk(bool enable)
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{
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if (enable == true) {
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DPORT_REG_SET_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
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} else {
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DPORT_REG_CLR_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
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}
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}
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void emac_dma_init(void)
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{
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_FWD_UNDER_GF);
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REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_OPT_SECOND_FRAME);
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REG_SET_FIELD(EMAC_DMABUSMODE_REG, EMAC_PROG_BURST_LEN, 4);
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}
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void emac_mac_enable_txrx(void)
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{
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REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_EMACRX);
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REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_EMACTX);
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}
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void emac_mac_init(void)
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{
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REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_EMACDUPLEX);
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REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_EMACMII);
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REG_CLR_BIT(EMAC_GMACCONFIG_REG, EMAC_EMACFESPEED);
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REG_SET_BIT(EMAC_GMACFF_REG, EMAC_PAM);
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}
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