a66df0826e
1. BIT(8) of CTRL is actually read-only bit indicating interrupt status 2. BIT(0) or CTRL had inverted meaning: 1 is “level”, 0 is “edge” 3. Add definitions of prescaler values
53 lines
2.3 KiB
C
53 lines
2.3 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_FRC_TIMER_REG_H_
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#define _SOC_FRC_TIMER_REG_H_
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#include "soc.h"
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/**
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* These are the register definitions for "legacy" timers
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*/
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#define REG_FRC_TIMER_BASE(i) (DR_REG_FRC_TIMER_BASE + i*0x20)
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#define FRC_TIMER_LOAD_REG(i) (REG_FRC_TIMER_BASE(i) + 0x0) // timer load value (23 bit for i==0, 32 bit for i==1)
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#define FRC_TIMER_LOAD_VALUE(i) ((i == 0)?0x007FFFFF:0xffffffff)
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#define FRC_TIMER_LOAD_VALUE_S 0
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#define FRC_TIMER_COUNT_REG(i) (REG_FRC_TIMER_BASE(i) + 0x4) // timer count value (23 bit for i==0, 32 bit for i==1)
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#define FRC_TIMER_COUNT ((i == 0)?0x007FFFFF:0xffffffff)
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#define FRC_TIMER_COUNT_S 0
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#define FRC_TIMER_CTRL_REG(i) (REG_FRC_TIMER_BASE(i) + 0x8)
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#define FRC_TIMER_INT_STATUS (BIT(8)) // interrupt status (RO)
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#define FRC_TIMER_ENABLE (BIT(7)) // enable timer
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#define FRC_TIMER_AUTOLOAD (BIT(6)) // enable autoload
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#define FRC_TIMER_PRESCALER 0x00000007
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#define FRC_TIMER_PRESCALER_S 1
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#define FRC_TIMER_PRESCALER_1 (0 << FRC_TIMER_PRESCALER_S)
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#define FRC_TIMER_PRESCALER_16 (2 << FRC_TIMER_PRESCALER_S)
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#define FRC_TIMER_PRESCALER_256 (4 << FRC_TIMER_PRESCALER_S)
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#define FRC_TIMER_LEVEL_INT (BIT(0)) // 1: level, 0: edge
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#define FRC_TIMER_INT_REG(i) (REG_FRC_TIMER_BASE(i) + 0xC)
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#define FRC_TIMER_INT_CLR (BIT(0)) // clear interrupt
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#define FRC_TIMER_ALARM_REG(i) (REG_FRC_TIMER_BASE(i) + 0x10) // timer alarm value; register only present for i == 1
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#define FRC_TIMER_ALARM 0xFFFFFFFF
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#define FRC_TIMER_ALARM_S 0
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#endif //_SOC_FRC_TIMER_REG_H_
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