142 lines
5 KiB
C
142 lines
5 KiB
C
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "string.h"
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#include "esp_spi_flash.h"
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//Errors that can be returned
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#define MMU_SET_ADDR_ALIGNED_ERROR 1
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#define MMU_SET_PAGE_SIZE_ERROR 3
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#define MMU_SET_VADDR_OUT_RANGE 5
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#define PROCACHE_MMU_ADDR_BASE 0x3FF10000
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#define APPCACHE_MMU_ADDR_BASE 0x3FF12000
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//sram
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#define PRO_DRAM1_START_ADDR 0x3F800000
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#define PRO_DRAM1_END_ADDR(psize) (PRO_DRAM1_START_ADDR + ((psize) << 17))
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//cache mmu register file address
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#define CACHE_MMU_ADDRESS_BASE(cpu_no) ((cpu_no) ? (APPCACHE_MMU_ADDR_BASE) : (PROCACHE_MMU_ADDR_BASE))
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//virtual address, physical address check
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#define ADDRESS_CHECK(addr,psize) (((addr) & (0xFFFF >>((64/(psize))-1))) != 0)
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//CPU number check
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#define CPU_NUMBER_CHECK(cpu_no) (((cpu_no)<0) || ((cpu_no)>1))
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//PID check
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#define PID_CHECK(pid) (((pid)<0) || ((pid)>7))
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//flash MMU edge check (flash size default : 16*1024 K)
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#define FLASH_MMU_EDGE_CHECK(mmu_val,num) (((mmu_val) + (num)) > 256)
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//sram MMU edge check (sram size default : 8*1024 K)
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#define SRAM_MMU_EDGE_CHECK(mmu_val,num,psize) (((mmu_val) + (num)) > ((8*1024)/(psize)))
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//We can relegate to the ROM version if the 2nd core isn't running (yet) and the RTOS is not started yet, for instance
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//in the bootloader and in the app start process. The ROM code manually disables the cache, without using
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//cache guards.
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unsigned int cache_sram_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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#ifndef BOOTLOADER_BUILD
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/*
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Note that this function is a replacement for the ROM function with the same name, with these differences:
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- It uses the DPORT workarounds
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- It fixes a bug where the ROM version throws an error when vaddr is more than 2MiB into the memory region
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- It uses the SPI cache guards to make sure the MMU is idle
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*/
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unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
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{
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const spi_flash_guard_funcs_t *guard=spi_flash_guard_get();
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if (!guard) {
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//Still starting up; guards not available yet. Use ROM version of code.
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return cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
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}
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unsigned int i,shift,mask_s;
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unsigned int mmu_addr;
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unsigned int mmu_table_val;
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//address check
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if( (ADDRESS_CHECK(vaddr,psize)) || (ADDRESS_CHECK(paddr,psize)) ){
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return MMU_SET_ADDR_ALIGNED_ERROR;
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}
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//psize check
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if(psize == 32) {
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shift = 15;
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mask_s = 0;
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} else if(psize == 16) {
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shift = 14;
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mask_s = 1;
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} else if(psize == 8) {
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shift = 13;
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mask_s = 2;
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} else if(psize == 4) {
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shift = 12;
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mask_s = 3;
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} else if(psize == 2) {
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shift = 11;
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mask_s = 4;
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} else {
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return MMU_SET_PAGE_SIZE_ERROR;
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}
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//mmu value
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mmu_table_val = paddr >> shift;
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//mmu_addr
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if(pid == 0 || pid == 1){
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if(vaddr >= PRO_DRAM1_START_ADDR && vaddr < PRO_DRAM1_END_ADDR(psize)){
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mmu_addr = 1152 + ((vaddr & (0x3FFFFF >> mask_s)) >> shift);
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} else{
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return MMU_SET_VADDR_OUT_RANGE;
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}
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} else {
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if(vaddr >= PRO_DRAM1_START_ADDR && vaddr < PRO_DRAM1_END_ADDR(psize)){
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mmu_addr = (1024 + (pid<<7)) + ((vaddr & (0x3FFFFF >> mask_s)) >> shift);
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} else{
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return MMU_SET_VADDR_OUT_RANGE;
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}
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}
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//The MMU registers are implemented in such a way that lookups from the cache subsystem may collide with
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//CPU access to the MMU registers. We use the flash guards to make sure the cache is disabled.
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guard->start();
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//mmu change
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for ( i = 0; i < num; i++){
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*(volatile unsigned int *)(CACHE_MMU_ADDRESS_BASE(cpu_no) + mmu_addr * 4) = mmu_table_val + i; //write table
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mmu_addr++;
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}
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if(cpu_no == 0){
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DPORT_REG_SET_FIELD(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, mask_s);
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} else {
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DPORT_REG_SET_FIELD(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, mask_s);
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}
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guard->end();
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return 0;
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}
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#else
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//For the bootloader, we can always use the ROM version of this: it works well enough and keeps the size of the bootloader binary down.
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unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num) {
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return cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
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}
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#endif
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