657 lines
No EOL
23 KiB
C
657 lines
No EOL
23 KiB
C
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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Tests for the adc device driver
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*/
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#include "esp_system.h"
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#include "esp_intr_alloc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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#include "driver/adc.h"
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#include "driver/dac.h"
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#include "driver/rtc_io.h"
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#include "driver/gpio.h"
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#include "unity.h"
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#include "esp_system.h"
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#include "esp_event.h"
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#include "esp_wifi.h"
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#include "esp_log.h"
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#include "nvs_flash.h"
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#include "test_utils.h"
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#include "soc/spi_reg.h"
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#include "soc/adc_periph.h"
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#include "test/test_common_adc.h"
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#if !DISABLED_FOR_TARGETS(ESP8266, ESP32) // This testcase for ESP32S2
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#include "soc/system_reg.h"
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#include "soc/lldesc.h"
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static const char *TAG = "test_adc";
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#define PLATFORM_SELECT (1) //0: pxp; 1: chip
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#if (PLATFORM_SELECT == 0) //PXP platform
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#include "soc/apb_ctrl_reg.h"
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#define SET_BREAK_POINT(flag) REG_WRITE(APB_CTRL_DATE_REG, flag)
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//PXP clk is slower.
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#define SYS_DELAY_TIME_MOM (1/40)
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#define RTC_SLOW_CLK_FLAG 1 // Slow clock is 32KHz.
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static void test_pxp_deinit_io(void)
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{
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for (int i = 0; i < 22; i++) {
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rtc_gpio_init(i);
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}
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}
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#else
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//PXP clk is slower.
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#define SET_BREAK_POINT(flag)
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#define SYS_DELAY_TIME_MOM (1)
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#define RTC_SLOW_CLK_FLAG 0 // Slow clock is 32KHz.
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#endif
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#define ADC_REG_BASE_TEST() ({ \
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TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(APB_SARADC_APB_CTRL_DATE_REG, APB_SARADC_APB_CTRL_DATE), APB_SARADC.apb_ctrl_date); \
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TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(SENS_SARDATE_REG, SENS_SAR_DATE), SENS.sardate.sar_date); \
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TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(RTC_IO_DATE_REG, RTC_IO_IO_DATE), RTCIO.date.date); \
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})
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/** Sample rate = APB_CLK(80 MHz) / (CLK_DIV + 1) / TRIGGER_INTERVAL / 2. */
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#define TEST_ADC_TRIGGER_INTERVAL_DEFAULT (40)
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#define TEST_ADC_DIGI_CLK_DIV_DEFAULT (9)
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static uint8_t adc_test_num = 9;
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static adc_channel_t adc_list[SOC_ADC_PATT_LEN_MAX] = {
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ADC_CHANNEL_0,
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ADC_CHANNEL_1,
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ADC_CHANNEL_2,
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ADC_CHANNEL_3,
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ADC_CHANNEL_4,
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ADC_CHANNEL_5,
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ADC_CHANNEL_6,
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// ADC_CHANNEL_7, // Workaround: IO18 is pullup outside in ESP32S2-Saola Runner.
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ADC_CHANNEL_8,
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ADC_CHANNEL_9,
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};
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/* For ESP32S2, it should use same atten, or, it will have error. */
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#define TEST_ADC_ATTEN_DEFAULT (ADC_ATTEN_11db)
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/*******************************************/
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/** SPI DMA INIT CODE */
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/*******************************************/
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extern esp_err_t adc_digi_reset(void);
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/* Work mode.
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* single: eof_num;
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* double: SAR_EOF_NUMBER/2;
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* alter: eof_num;
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* */
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#define SAR_SIMPLE_NUM 512 // Set sample number of enabled unit.
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/* Use two DMA linker to save ADC data. ADC sample 1 times -> 2 byte data -> 2 DMA link buf. */
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#define SAR_DMA_DATA_SIZE(unit, sample_num) (SAR_EOF_NUMBER(unit, sample_num)) //
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#define SAR_EOF_NUMBER(unit, sample_num) ((sample_num) * (unit))
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#define SAR_MEAS_LIMIT_NUM(unit, sample_num) (SAR_SIMPLE_NUM)
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#define SAR_SIMPLE_TIMEOUT_MS 1000
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typedef struct dma_msg {
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uint32_t int_msk;
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uint8_t *data;
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uint32_t data_len;
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} adc_dma_event_t;
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static uint8_t link_buf[2][SAR_DMA_DATA_SIZE(2, SAR_SIMPLE_NUM)] = {0};
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static lldesc_t dma1 = {0};
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static lldesc_t dma2 = {0};
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static bool adc_dma_flag = false;
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static QueueHandle_t que_adc = NULL;
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static adc_dma_event_t adc_evt;
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/** ADC-DMA ISR handler. */
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static IRAM_ATTR void adc_dma_isr(void *arg)
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{
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uint32_t int_st = REG_READ(SPI_DMA_INT_ST_REG(3));
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int task_awoken = pdFALSE;
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REG_WRITE(SPI_DMA_INT_CLR_REG(3), int_st);
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if (int_st & SPI_IN_SUC_EOF_INT_ST_M) {
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adc_evt.int_msk = int_st;
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xQueueSendFromISR(que_adc, &adc_evt, &task_awoken);
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}
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if (int_st & SPI_IN_DONE_INT_ST) {
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adc_evt.int_msk = int_st;
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xQueueSendFromISR(que_adc, &adc_evt, &task_awoken);
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}
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ESP_EARLY_LOGV(TAG, "int msk%x\n", int_st);
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if (task_awoken == pdTRUE) {
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portYIELD_FROM_ISR();
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}
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}
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/** Register ADC-DMA handler. */
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static esp_err_t adc_dma_isr_register(void (*fun)(void *), void *arg)
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{
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esp_err_t ret = ESP_FAIL;
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ret = esp_intr_alloc(ETS_SPI3_DMA_INTR_SOURCE, 0, fun, arg, NULL);
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return ret;
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}
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/** Reset DMA linker pointer and start DMA. */
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static void dma_linker_restart(void)
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{
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START);
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SET_PERI_REG_BITS(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_ADDR, (uint32_t)&dma1, 0);
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REG_SET_BIT(SPI_DMA_CONF_REG(3), SPI_IN_RST);
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REG_CLR_BIT(SPI_DMA_CONF_REG(3), SPI_IN_RST);
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REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP);
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REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START);
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}
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/**
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* DMA liner initialization and start.
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* @param is_loop
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* - true: The two dma linked lists are connected end to end, with no end mark (eof).
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* - false: The two dma linked lists are connected end to end, with end mark (eof).
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* @param int_mask DMA interrupt types.
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*/
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static void dma_linker_init(adc_unit_t adc, bool is_loop, uint32_t int_mask)
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{
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dma1 = (lldesc_t) {
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.size = SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
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.owner = 1,
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.buf = &link_buf[0][0],
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.qe.stqe_next = &dma2,
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};
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dma2 = (lldesc_t) {
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.size = SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
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.owner = 1,
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.buf = &link_buf[1][0],
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};
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if (is_loop) {
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dma2.qe.stqe_next = &dma1;
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} else {
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dma2.qe.stqe_next = NULL;
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}
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_APB_SARADC_CLK_EN_M);
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_DMA_CLK_EN_M);
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REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN);
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REG_CLR_BIT(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_DMA_RST_M);
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REG_CLR_BIT(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST_M);
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if (!adc_dma_flag) {
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que_adc = xQueueCreate(5, sizeof(adc_dma_event_t));
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adc_dma_isr_register(adc_dma_isr, NULL);
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adc_dma_flag = true;
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}
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REG_WRITE(SPI_DMA_INT_CLR_REG(3), 0xFFFFFFFF);
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REG_WRITE(SPI_DMA_INT_ENA_REG(3), int_mask);
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dma_linker_restart();
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printf("reg addr 0x%08x 0x%08x \n", SPI_DMA_IN_LINK_REG(3), (uint32_t)&dma1);
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}
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/*******************************************/
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/** SPI DMA INIT CODE END */
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/*******************************************/
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#define DEBUG_CHECK_ENABLE 1
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#define DEBUG_PRINT_ENABLE 1
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#define DEBUG_CHECK_ERROR 10
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/**
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* Check the ADC-DMA data in linker buffer by input level.
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* ideal_level
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* - -1: Don't check data.
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* - 0: ADC channel voltage is 0v.
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* - 1: ADC channel voltage is 3.3v.
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* - 2: ADC channel voltage is 1.4v.
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*/
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static esp_err_t adc_dma_data_check(adc_unit_t adc, int ideal_level)
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{
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int unit_old = 1;
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int ch_cnt = 0;
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for (int cnt = 0; cnt < 2; cnt++) {
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ets_printf("\n[%s] link_buf[%d]: \n", __func__, cnt % 2);
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for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i += 2) {
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uint8_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
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uint16_t temp = (h << 8 | l);
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adc_digi_output_data_t *data = (adc_digi_output_data_t *)&temp;
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if (adc > ADC_UNIT_2) { //ADC_ENCODE_11BIT
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#if DEBUG_PRINT_ENABLE
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if (i % 16 == 0) {
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ets_printf("\n");
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}
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ets_printf("[%d_%d_%04x] ", data->type2.unit, data->type2.channel, data->type2.data);
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#endif
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#if DEBUG_CHECK_ENABLE
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if (ideal_level >= 0) {
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TEST_ASSERT_NOT_EQUAL(unit_old, data->type2.unit);
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unit_old = data->type2.unit;
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if (data->type2.channel > ADC_CHANNEL_MAX) {
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printf("Data invalid [%d]\n", data->type2.channel);
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continue;
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}
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int cur_ch = ((ch_cnt++ / 2) % adc_test_num);
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TEST_ASSERT_EQUAL( data->type2.channel, adc_list[cur_ch] );
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}
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if (ideal_level == 1) { // high level 3.3v
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TEST_ASSERT_EQUAL( 0x7FF, data->type2.data );
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} else if (ideal_level == 0) { // low level 0v
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TEST_ASSERT_LESS_THAN( 10, data->type2.data );
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} else if (ideal_level == 2) { // middle level 1.4v
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TEST_ASSERT_INT_WITHIN( 128, 1100, data->type2.data );
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} else if (ideal_level == 3) { // normal level
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} else { // no check
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}
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#endif
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} else { //ADC_ENCODE_12BIT
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#if DEBUG_PRINT_ENABLE
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if (i % 16 == 0) {
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ets_printf("\n");
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}
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ets_printf("[%d_%04x] ", data->type1.channel, data->type1.data);
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#endif
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#if DEBUG_CHECK_ENABLE
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if (ideal_level >= 0) {
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int cur_ch = ((ch_cnt++) % adc_test_num);
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TEST_ASSERT_EQUAL( adc_list[cur_ch], data->type1.channel );
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}
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if (ideal_level == 1) { // high level 3.3v
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TEST_ASSERT_EQUAL( 0XFFF, data->type1.data );
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} else if (ideal_level == 0) { // low level 0v
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TEST_ASSERT_LESS_THAN( 10, data->type1.data );
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} else if (ideal_level == 2) { // middle level 1.4v
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TEST_ASSERT_INT_WITHIN( 256, 2200, data->type1.data );
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} else if (ideal_level == 3) { // normal level
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} else { // no check
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}
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#endif
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}
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link_buf[cnt % 2][i] = 0;
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link_buf[cnt % 2][i + 1] = 0;
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}
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ets_printf("\n");
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}
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return ESP_OK;
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}
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static esp_err_t adc_dma_data_multi_st_check(adc_unit_t adc)
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{
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adc_dma_event_t evt;
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ESP_LOGI(TAG, "adc IO normal, test ...");
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for (int i = 0; i < adc_test_num; i++) {
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adc_io_normal(adc, adc_list[i]);
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}
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TEST_ESP_OK( adc_digi_start() );
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while (1) {
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TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
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if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
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break;
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}
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}
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TEST_ESP_OK( adc_digi_stop() );
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dma_linker_restart();
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adc_digi_reset();
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TEST_ESP_OK( adc_dma_data_check(adc, -1) ); // Don't check data.
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ESP_LOGI(TAG, "adc IO fake tie high, test ...");
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for (int i = 0; i < adc_test_num; i++) {
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adc_fake_tie_high(adc, adc_list[i]);
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}
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TEST_ESP_OK( adc_digi_start() );
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while (1) {
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TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
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if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
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break;
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}
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}
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TEST_ESP_OK( adc_digi_stop() );
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dma_linker_restart();
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adc_digi_reset();
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TEST_ESP_OK( adc_dma_data_check(adc, 1) );
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ESP_LOGI(TAG, "adc IO fake tie low, test ...");
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for (int i = 0; i < adc_test_num; i++) {
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adc_fake_tie_low(adc, adc_list[i]);
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}
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TEST_ESP_OK( adc_digi_start() );
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while (1) {
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TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
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if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
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break;
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}
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}
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TEST_ESP_OK( adc_digi_stop() );
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dma_linker_restart();
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adc_digi_reset();
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TEST_ESP_OK( adc_dma_data_check(adc, 0) );
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ESP_LOGI(TAG, "adc IO fake tie middle, test ...");
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for (int i = 0; i < adc_test_num; i++) {
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adc_fake_tie_middle(adc, adc_list[i]);
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}
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TEST_ESP_OK( adc_digi_start() );
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while (1) {
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TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
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if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
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break;
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}
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}
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TEST_ESP_OK( adc_digi_stop() );
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dma_linker_restart();
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adc_digi_reset();
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TEST_ESP_OK( adc_dma_data_check(adc, 2) );
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return ESP_OK;
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}
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#include "soc/apb_saradc_struct.h"
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/**
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* Test the partten table setting. It's easy wrong.
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*
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* @param adc_n ADC unit.
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* @param in_partten_len The length of partten be set.
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* @param in_last_ch The channel number of the last message.
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*/
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static esp_err_t adc_check_patt_table(adc_unit_t adc, uint32_t in_partten_len, adc_channel_t in_last_ch)
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{
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esp_err_t ret = ESP_FAIL;
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uint8_t index = (in_partten_len - 1) / 4;
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uint8_t offset = 24 - ((in_partten_len - 1) % 4) * 8;
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uint32_t temp = 0, len;
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if (adc & ADC_UNIT_1) {
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len = APB_SARADC.ctrl.sar1_patt_len + 1;
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temp = APB_SARADC.sar1_patt_tab[index];
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printf("patt1 len %d\n", len);
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printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[0]);
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printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[1]);
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printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[2]);
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printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[3]);
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if (in_partten_len == len) {
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if (in_last_ch == (((temp >> (offset + 4))) & 0xf)) {
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ret = ESP_OK;
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}
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}
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}
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if (adc & ADC_UNIT_2) {
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len = APB_SARADC.ctrl.sar2_patt_len + 1;
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temp = APB_SARADC.sar2_patt_tab[index];
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printf("patt2 len %d\n", len);
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printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[0]);
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printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[1]);
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printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[2]);
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printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[3]);
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if (in_partten_len == len) {
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if (in_last_ch == (((temp >> (offset + 4))) & 0xf)) {
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ret = ESP_OK;
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}
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}
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}
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return ret;
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}
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/**
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* Testcase: Check the base function of ADC-DMA. Include:
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* - Various conversion modes.
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* - Whether the channel and data are lost.
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* - Whether the data is the same as the channel voltage.
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*/
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int test_adc_dig_dma_single_unit(adc_unit_t adc)
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{
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ESP_LOGI(TAG, " >> %s << ", __func__);
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ESP_LOGI(TAG, " >> adc unit: %x << ", adc);
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TEST_ESP_OK( adc_digi_init() );
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/* arbiter config */
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adc_arbiter_t arb_cfg = {
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.mode = ADC_ARB_MODE_FIX,
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.dig_pri = 0,
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.pwdet_pri = 2,
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.rtc_pri = 1,
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};
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TEST_ESP_OK( adc_arbiter_config(ADC_UNIT_2, &arb_cfg) ); // If you want use force
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adc_digi_config_t config = {
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.conv_limit_en = false,
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.conv_limit_num = 0,
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.interval = TEST_ADC_TRIGGER_INTERVAL_DEFAULT,
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.dig_clk.use_apll = 0, // APB clk
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.dig_clk.div_num = TEST_ADC_DIGI_CLK_DIV_DEFAULT,
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.dig_clk.div_b = 0,
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.dig_clk.div_a = 0,
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.dma_eof_num = SAR_EOF_NUMBER((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
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};
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/* Config pattern table */
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adc_digi_pattern_table_t adc1_patt[SOC_ADC_PATT_LEN_MAX] = {0};
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adc_digi_pattern_table_t adc2_patt[SOC_ADC_PATT_LEN_MAX] = {0};
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if (adc & ADC_UNIT_1) {
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config.adc1_pattern_len = adc_test_num;
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config.adc1_pattern = adc1_patt;
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for (int i = 0; i < adc_test_num; i++) {
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adc1_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
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adc1_patt[i].channel = adc_list[i];
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adc_gpio_init(ADC_UNIT_1, adc_list[i]);
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}
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}
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if (adc & ADC_UNIT_2) {
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config.adc2_pattern_len = adc_test_num;
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config.adc2_pattern = adc2_patt;
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for (int i = 0; i < adc_test_num; i++) {
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adc2_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
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adc2_patt[i].channel = adc_list[i];
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adc_gpio_init(ADC_UNIT_2, adc_list[i]);
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}
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}
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if (adc == ADC_UNIT_1) {
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config.conv_mode = ADC_CONV_SINGLE_UNIT_1;
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config.format = ADC_DIGI_FORMAT_12BIT;
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} else if (adc == ADC_UNIT_2) {
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config.conv_mode = ADC_CONV_SINGLE_UNIT_2;
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config.format = ADC_DIGI_FORMAT_12BIT;
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} else if (adc == ADC_UNIT_BOTH) {
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config.conv_mode = ADC_CONV_BOTH_UNIT;
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config.format = ADC_DIGI_FORMAT_11BIT;
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} else if (adc == ADC_UNIT_ALTER) {
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config.conv_mode = ADC_CONV_ALTER_UNIT;
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config.format = ADC_DIGI_FORMAT_11BIT;
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}
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TEST_ESP_OK( adc_digi_controller_config(&config) );
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dma_linker_init(adc, false, SPI_IN_SUC_EOF_INT_ENA);
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TEST_ESP_OK( adc_check_patt_table(adc, adc_test_num, adc_list[adc_test_num - 1]) );
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adc_dma_data_multi_st_check(adc);
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TEST_ESP_OK( adc_digi_deinit() );
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return 0;
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}
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TEST_CASE("ADC DMA single read", "[ADC]")
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{
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test_adc_dig_dma_single_unit(ADC_UNIT_BOTH);
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|
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test_adc_dig_dma_single_unit(ADC_UNIT_ALTER);
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|
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test_adc_dig_dma_single_unit(ADC_UNIT_1);
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|
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test_adc_dig_dma_single_unit(ADC_UNIT_2);
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}
|
|
|
|
#include "touch_scope.h"
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|
/**
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* 0: ADC1 channels raw data debug.
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|
* 1: ADC2 channels raw data debug.
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* 2: ADC1 one channel raw data debug.
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*/
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|
#define SCOPE_DEBUG_TYPE 0
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|
#define SCOPE_DEBUG_CHANNEL_MAX (10)
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|
#define SCOPE_DEBUG_ENABLE (0)
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#define SCOPE_UART_BUADRATE (256000)
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|
#define SCOPE_DEBUG_FREQ_MS (50)
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#define SCOPE_OUTPUT_UART (0)
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static float scope_temp[SCOPE_DEBUG_CHANNEL_MAX] = {0}; // max scope channel is 10.
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|
|
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int test_adc_dig_scope_debug_unit(adc_unit_t adc)
|
|
{
|
|
ESP_LOGI(TAG, " >> %s << ", __func__);
|
|
ESP_LOGI(TAG, " >> adc unit: %x << ", adc);
|
|
|
|
TEST_ESP_OK( adc_digi_init() );
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|
if (adc & ADC_UNIT_2) {
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|
/* arbiter config */
|
|
adc_arbiter_t arb_cfg = {
|
|
.mode = ADC_ARB_MODE_FIX,
|
|
.dig_pri = 0,
|
|
.pwdet_pri = 2,
|
|
.rtc_pri = 1,
|
|
};
|
|
TEST_ESP_OK( adc_arbiter_config(ADC_UNIT_2, &arb_cfg) ); // If you want use force
|
|
}
|
|
adc_digi_config_t config = {
|
|
.conv_limit_en = false,
|
|
.conv_limit_num = 0,
|
|
.interval = TEST_ADC_TRIGGER_INTERVAL_DEFAULT,
|
|
.dig_clk.use_apll = 0, // APB clk
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|
.dig_clk.div_num = TEST_ADC_DIGI_CLK_DIV_DEFAULT,
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|
.dig_clk.div_a = 0,
|
|
.dig_clk.div_b = 0,
|
|
.dma_eof_num = SAR_EOF_NUMBER((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
|
|
};
|
|
/* Config pattern table */
|
|
adc_digi_pattern_table_t adc1_patt[SOC_ADC_PATT_LEN_MAX] = {0};
|
|
adc_digi_pattern_table_t adc2_patt[SOC_ADC_PATT_LEN_MAX] = {0};
|
|
if (adc & ADC_UNIT_1) {
|
|
config.adc1_pattern_len = adc_test_num;
|
|
config.adc1_pattern = adc1_patt;
|
|
for (int i = 0; i < adc_test_num; i++) {
|
|
adc1_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
|
|
adc1_patt[i].channel = adc_list[i];
|
|
adc_gpio_init(ADC_UNIT_1, adc_list[i]);
|
|
}
|
|
}
|
|
if (adc & ADC_UNIT_2) {
|
|
config.adc2_pattern_len = adc_test_num;
|
|
config.adc2_pattern = adc2_patt;
|
|
for (int i = 0; i < adc_test_num; i++) {
|
|
adc2_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
|
|
adc2_patt[i].channel = adc_list[i];
|
|
adc_gpio_init(ADC_UNIT_2, adc_list[i]);
|
|
}
|
|
}
|
|
if (adc == ADC_UNIT_1) {
|
|
config.conv_mode = ADC_CONV_SINGLE_UNIT_1;
|
|
config.format = ADC_DIGI_FORMAT_12BIT;
|
|
} else if (adc == ADC_UNIT_2) {
|
|
config.conv_mode = ADC_CONV_SINGLE_UNIT_2;
|
|
config.format = ADC_DIGI_FORMAT_12BIT;
|
|
} else if (adc == ADC_UNIT_BOTH) {
|
|
config.conv_mode = ADC_CONV_BOTH_UNIT;
|
|
config.format = ADC_DIGI_FORMAT_11BIT;
|
|
} else if (adc == ADC_UNIT_ALTER) {
|
|
config.conv_mode = ADC_CONV_ALTER_UNIT;
|
|
config.format = ADC_DIGI_FORMAT_11BIT;
|
|
}
|
|
TEST_ESP_OK( adc_digi_controller_config(&config) );
|
|
|
|
dma_linker_init(adc, false, SPI_IN_DONE_INT_ENA & SPI_IN_SUC_EOF_INT_ENA);
|
|
|
|
ESP_LOGI(TAG, "adc IO fake tie middle, test ...");
|
|
for (int i = 0; i < adc_test_num; i++) {
|
|
adc_fake_tie_middle(adc, adc_list[i]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void scope_output(int adc_num, int channel, int data)
|
|
{
|
|
/** can replace by uart log.*/
|
|
#if SCOPE_OUTPUT_UART
|
|
static int icnt = 0;
|
|
if (icnt++ % 8 == 0) {
|
|
ets_printf("\n");
|
|
}
|
|
ets_printf("[%d_%d_%04x] ", adc_num, channel, data);
|
|
return;
|
|
#endif
|
|
#if SCOPE_DEBUG_TYPE == 0
|
|
if (adc_num != 0) {
|
|
return;
|
|
}
|
|
#elif SCOPE_DEBUG_TYPE == 1
|
|
if (adc_num != 1) {
|
|
return;
|
|
}
|
|
#endif
|
|
int i;
|
|
/* adc Read */
|
|
for (i = 0; i < adc_test_num; i++) {
|
|
if (adc_list[i] == channel && scope_temp[i] == 0) {
|
|
scope_temp[i] = data;
|
|
break;
|
|
}
|
|
}
|
|
if (i == adc_test_num) {
|
|
test_tp_print_to_scope(scope_temp, adc_test_num);
|
|
vTaskDelay(SCOPE_DEBUG_FREQ_MS / portTICK_RATE_MS);
|
|
for (int i = 0; i < adc_test_num; i++) {
|
|
scope_temp[i] = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Manual test: Capture ADC-DMA data and display it on the serial oscilloscope. Used to observe the stability of the data.
|
|
* Use step:
|
|
* 1. Run this test from the unit test app.
|
|
* 2. Use `ESP-Tuning Tool`(download from `www.espressif.com`) to capture.
|
|
* 3. The readings of multiple channels will be displayed on the tool.
|
|
*/
|
|
TEST_CASE("test_adc_digi_slope_debug", "[adc_dma][ignore]")
|
|
{
|
|
adc_dma_event_t evt;
|
|
test_tp_scope_debug_init(0, -1, -1, SCOPE_UART_BUADRATE);
|
|
adc_unit_t adc = ADC_CONV_BOTH_UNIT;
|
|
test_adc_dig_scope_debug_unit(adc);
|
|
while (1) {
|
|
TEST_ESP_OK( adc_digi_start() );
|
|
TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, portMAX_DELAY), pdTRUE );
|
|
if (evt.int_msk & SPI_IN_SUC_EOF_INT_ST) {
|
|
TEST_ESP_OK( adc_digi_stop() );
|
|
dma_linker_restart();
|
|
adc_digi_reset();
|
|
for (int cnt = 0; cnt < 2; cnt++) {
|
|
ets_printf("cnt%d\n", cnt);
|
|
for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i += 2) {
|
|
uint8_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
|
|
uint16_t temp = (h << 8 | l);
|
|
adc_digi_output_data_t *data = (adc_digi_output_data_t *)&temp;
|
|
if (adc > ADC_UNIT_2) { //ADC_ENCODE_11BIT
|
|
scope_output(data->type2.unit, data->type2.channel, data->type2.data);
|
|
} else { //ADC_ENCODE_12BIT
|
|
if (adc == ADC_UNIT_1) {
|
|
scope_output(0, data->type1.channel, data->type1.data);
|
|
} else if (adc == ADC_UNIT_2) {
|
|
scope_output(1, data->type1.channel, data->type1.data);
|
|
}
|
|
}
|
|
link_buf[cnt % 2][i] = 0;
|
|
link_buf[cnt % 2][i + 1] = 0;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif // !DISABLED_FOR_TARGETS(ESP8266, ESP32)
|