fdf983e0c4
The SPI bus lock on SPI1 introduces two side effects:
1. The device lock for the main flash requires the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` to be selected, however this
option is disabled by default in earlier IDF versions. Some developers
may find their project cannot be built by their old sdkconfig files.
2. Usually we don't need the lock on the SPI1 bus, due to it's
restrictions. However the overhead still exists in this case, the IRAM
cost for static version of semaphore functions, and the time cost when
getting and releasing the lock.
This commit:
1. Add a CONFIG_SPI_FLASH_BYPASS_MAIN_LOCK option, which will forbid the
space cost, as well as the initialization of the main bus lock.
2. When the option is not selected, the bus lock is used, the
`CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION` will be selected explicitly.
3. Revert default value of `CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION`
to `n`.
introduced in 49a48644e4.
Closes https://github.com/espressif/esp-idf/issues/5046
116 lines
3 KiB
C
116 lines
3 KiB
C
/* SPI Master Half Duplex EEPROM example.
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This example code is in the Public Domain (or CC0 licensed, at your option.)
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Unless required by applicable law or agreed to in writing, this
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software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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CONDITIONS OF ANY KIND, either express or implied.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "driver/spi_master.h"
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#include "driver/gpio.h"
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "spi_eeprom.h"
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/*
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This code demonstrates how to use the SPI master half duplex mode to read/write a AT932C46D EEPROM (8-bit mode).
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32
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# ifdef CONFIG_EXAMPLE_USE_SPI1_PINS
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# define EEPROM_HOST SPI1_HOST
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# define DMA_CHAN 0
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// Use default pins, same as the flash chip.
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# define PIN_NUM_MISO 7
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# define PIN_NUM_MOSI 8
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# define PIN_NUM_CLK 6
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# else
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# define EEPROM_HOST HSPI_HOST
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# define DMA_CHAN 2
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# define PIN_NUM_MISO 18
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# define PIN_NUM_MOSI 23
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# define PIN_NUM_CLK 19
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# endif
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# define PIN_NUM_CS 13
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#elif defined CONFIG_IDF_TARGET_ESP32S2
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# define EEPROM_HOST SPI2_HOST
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# define DMA_CHAN EEPROM_HOST
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# define PIN_NUM_MISO 37
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# define PIN_NUM_MOSI 35
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# define PIN_NUM_CLK 36
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# define PIN_NUM_CS 34
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#endif
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static const char TAG[] = "main";
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void app_main(void)
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{
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esp_err_t ret;
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#ifndef CONFIG_EXAMPLE_USE_SPI1_PINS
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ESP_LOGI(TAG, "Initializing bus SPI%d...", EEPROM_HOST+1);
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spi_bus_config_t buscfg={
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.miso_io_num = PIN_NUM_MISO,
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.mosi_io_num = PIN_NUM_MOSI,
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.sclk_io_num = PIN_NUM_CLK,
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.quadwp_io_num = -1,
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.quadhd_io_num = -1,
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.max_transfer_sz = 32,
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};
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//Initialize the SPI bus
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ret = spi_bus_initialize(EEPROM_HOST, &buscfg, DMA_CHAN);
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ESP_ERROR_CHECK(ret);
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#else
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ESP_LOGI(TAG, "Attach to main flash bus...");
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#endif
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eeprom_config_t eeprom_config = {
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.cs_io = PIN_NUM_CS,
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.host = EEPROM_HOST,
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.miso_io = PIN_NUM_MISO,
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};
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#ifdef CONFIG_EXAMPLE_INTR_USED
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eeprom_config.intr_used = true;
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gpio_install_isr_service(0);
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#endif
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eeprom_handle_t eeprom_handle;
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ESP_LOGI(TAG, "Initializing device...");
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ret = spi_eeprom_init(&eeprom_config, &eeprom_handle);
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ESP_ERROR_CHECK(ret);
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ret = spi_eeprom_write_enable(eeprom_handle);
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ESP_ERROR_CHECK(ret);
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const char test_str[] = "Hello World!";
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ESP_LOGI(TAG, "Write: %s", test_str);
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for (int i = 0; i < sizeof(test_str); i++) {
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// No need for this EEPROM to erase before write.
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ret = spi_eeprom_write(eeprom_handle, i, test_str[i]);
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ESP_ERROR_CHECK(ret);
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}
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uint8_t test_buf[32] = "";
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for (int i = 0; i < sizeof(test_str); i++) {
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ret = spi_eeprom_read(eeprom_handle, i, &test_buf[i]);
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ESP_ERROR_CHECK(ret);
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}
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ESP_LOGI(TAG, "Read: %s", test_buf);
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ESP_LOGI(TAG, "Example finished.");
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while (1) {
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// Add your main loop handling code here.
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vTaskDelay(1);
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}
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}
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