580 lines
20 KiB
C
580 lines
20 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_I2S_REG_H_
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#define _SOC_I2S_REG_H_
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#include "soc.h"
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#define I2SCONF (DR_REG_I2S_BASE + 0x0008)
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#define I2S_I2S_SIG_LOOPBACK (BIT(18))
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#define I2S_I2S_SIG_LOOPBACK_S 18
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#define I2S_RX_MSB_RIGHT (BIT(17))
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#define I2S_RX_MSB_RIGHT_S 17
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#define I2S_TX_MSB_RIGHT (BIT(16))
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#define I2S_TX_MSB_RIGHT_S 16
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#define I2S_I2S_RX_MONO (BIT(15))
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#define I2S_I2S_RX_MONO_S 15
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#define I2S_I2S_TX_MONO (BIT(14))
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#define I2S_I2S_TX_MONO_S 14
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#define I2S_I2S_RX_SHORT_SYNC (BIT(13))
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#define I2S_I2S_RX_SHORT_SYNC_S 13
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#define I2S_I2S_TX_SHORT_SYNC (BIT(12))
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#define I2S_I2S_TX_SHORT_SYNC_S 12
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#define I2S_RX_MSB_SHIFT (BIT(11))
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#define I2S_RX_MSB_SHIFT_S 11
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#define I2S_TX_MSB_SHIFT (BIT(10))
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#define I2S_TX_MSB_SHIFT_S 10
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#define I2S_RX_RIGHT_FIRST (BIT(9))
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#define I2S_RX_RIGHT_FIRST_S 9
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#define I2S_TX_RIGHT_FIRST (BIT(8))
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#define I2S_TX_RIGHT_FIRST_S 8
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#define I2S_RX_SLAVE_MOD (BIT(7))
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#define I2S_RX_SLAVE_MOD_S 7
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#define I2S_TX_SLAVE_MOD (BIT(6))
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#define I2S_TX_SLAVE_MOD_S 6
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#define I2S_I2S_RX_START (BIT(5))
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#define I2S_I2S_RX_START_S 5
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#define I2S_I2S_TX_START (BIT(4))
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#define I2S_I2S_TX_START_S 4
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#define I2S_I2S_RX_FIFO_RESET (BIT(3))
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#define I2S_I2S_RX_FIFO_RESET_S 3
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#define I2S_I2S_TX_FIFO_RESET (BIT(2))
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#define I2S_I2S_TX_FIFO_RESET_S 2
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#define I2S_I2S_RX_RESET (BIT(1))
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#define I2S_I2S_RX_RESET_S 1
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#define I2S_I2S_TX_RESET (BIT(0))
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#define I2S_I2S_TX_RESET_S 0
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#define I2SINT_RAW (DR_REG_I2S_BASE + 0x000c)
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#define I2S_I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16))
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#define I2S_I2S_OUT_TOTAL_EOF_INT_RAW_S 16
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#define I2S_I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15))
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#define I2S_I2S_IN_DSCR_EMPTY_INT_RAW_S 15
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#define I2S_I2S_OUT_DSCR_ERR_INT_RAW (BIT(14))
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#define I2S_I2S_OUT_DSCR_ERR_INT_RAW_S 14
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#define I2S_I2S_IN_DSCR_ERR_INT_RAW (BIT(13))
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#define I2S_I2S_IN_DSCR_ERR_INT_RAW_S 13
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#define I2S_I2S_OUT_EOF_INT_RAW (BIT(12))
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#define I2S_I2S_OUT_EOF_INT_RAW_S 12
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#define I2S_I2S_OUT_DONE_INT_RAW (BIT(11))
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#define I2S_I2S_OUT_DONE_INT_RAW_S 11
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#define I2S_I2S_IN_ERR_EOF_INT_RAW (BIT(10))
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#define I2S_I2S_IN_ERR_EOF_INT_RAW_S 10
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#define I2S_I2S_IN_SUC_EOF_INT_RAW (BIT(9))
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#define I2S_I2S_IN_SUC_EOF_INT_RAW_S 9
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#define I2S_I2S_IN_DONE_INT_RAW (BIT(8))
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#define I2S_I2S_IN_DONE_INT_RAW_S 8
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#define I2S_I2S_TX_HUNG_INT_RAW (BIT(7))
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#define I2S_I2S_TX_HUNG_INT_RAW_S 7
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#define I2S_I2S_RX_HUNG_INT_RAW (BIT(6))
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#define I2S_I2S_RX_HUNG_INT_RAW_S 6
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#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
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#define I2S_I2S_TX_REMPTY_INT_RAW_S 5
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#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
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#define I2S_I2S_TX_WFULL_INT_RAW_S 4
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#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
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#define I2S_I2S_RX_REMPTY_INT_RAW_S 3
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#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
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#define I2S_I2S_RX_WFULL_INT_RAW_S 2
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#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
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#define I2S_I2S_TX_PUT_DATA_INT_RAW_S 1
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#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
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#define I2S_I2S_RX_TAKE_DATA_INT_RAW_S 0
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#define I2SINT_ST (DR_REG_I2S_BASE + 0x0010)
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#define I2S_I2S_OUT_TOTAL_EOF_INT_ST (BIT(16))
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#define I2S_I2S_OUT_TOTAL_EOF_INT_ST_S 16
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#define I2S_I2S_IN_DSCR_EMPTY_INT_ST (BIT(15))
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#define I2S_I2S_IN_DSCR_EMPTY_INT_ST_S 15
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#define I2S_I2S_OUT_DSCR_ERR_INT_ST (BIT(14))
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#define I2S_I2S_OUT_DSCR_ERR_INT_ST_S 14
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#define I2S_I2S_IN_DSCR_ERR_INT_ST (BIT(13))
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#define I2S_I2S_IN_DSCR_ERR_INT_ST_S 13
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#define I2S_I2S_OUT_EOF_INT_ST (BIT(12))
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#define I2S_I2S_OUT_EOF_INT_ST_S 12
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#define I2S_I2S_OUT_DONE_INT_ST (BIT(11))
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#define I2S_I2S_OUT_DONE_INT_ST_S 11
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#define I2S_I2S_IN_ERR_EOF_INT_ST (BIT(10))
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#define I2S_I2S_IN_ERR_EOF_INT_ST_S 10
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#define I2S_I2S_IN_SUC_EOF_INT_ST (BIT(9))
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#define I2S_I2S_IN_SUC_EOF_INT_ST_S 9
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#define I2S_I2S_IN_DONE_INT_ST (BIT(8))
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#define I2S_I2S_IN_DONE_INT_ST_S 8
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#define I2S_I2S_TX_HUNG_INT_ST (BIT(7))
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#define I2S_I2S_TX_HUNG_INT_ST_S 7
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#define I2S_I2S_RX_HUNG_INT_ST (BIT(6))
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#define I2S_I2S_RX_HUNG_INT_ST_S 6
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#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
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#define I2S_I2S_TX_REMPTY_INT_ST_S 5
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#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
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#define I2S_I2S_TX_WFULL_INT_ST_S 4
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#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
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#define I2S_I2S_RX_REMPTY_INT_ST_S 3
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#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
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#define I2S_I2S_RX_WFULL_INT_ST_S 2
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#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
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#define I2S_I2S_TX_PUT_DATA_INT_ST_S 1
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#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
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#define I2S_I2S_RX_TAKE_DATA_INT_ST_S 0
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#define I2SINT_ENA (DR_REG_I2S_BASE + 0x0014)
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#define I2S_I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16))
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#define I2S_I2S_OUT_TOTAL_EOF_INT_ENA_S 16
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#define I2S_I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15))
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#define I2S_I2S_IN_DSCR_EMPTY_INT_ENA_S 15
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#define I2S_I2S_OUT_DSCR_ERR_INT_ENA (BIT(14))
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#define I2S_I2S_OUT_DSCR_ERR_INT_ENA_S 14
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#define I2S_I2S_IN_DSCR_ERR_INT_ENA (BIT(13))
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#define I2S_I2S_IN_DSCR_ERR_INT_ENA_S 13
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#define I2S_I2S_OUT_EOF_INT_ENA (BIT(12))
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#define I2S_I2S_OUT_EOF_INT_ENA_S 12
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#define I2S_I2S_OUT_DONE_INT_ENA (BIT(11))
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#define I2S_I2S_OUT_DONE_INT_ENA_S 11
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#define I2S_I2S_IN_ERR_EOF_INT_ENA (BIT(10))
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#define I2S_I2S_IN_ERR_EOF_INT_ENA_S 10
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#define I2S_I2S_IN_SUC_EOF_INT_ENA (BIT(9))
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#define I2S_I2S_IN_SUC_EOF_INT_ENA_S 9
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#define I2S_I2S_IN_DONE_INT_ENA (BIT(8))
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#define I2S_I2S_IN_DONE_INT_ENA_S 8
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#define I2S_I2S_TX_HUNG_INT_ENA (BIT(7))
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#define I2S_I2S_TX_HUNG_INT_ENA_S 7
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#define I2S_I2S_RX_HUNG_INT_ENA (BIT(6))
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#define I2S_I2S_RX_HUNG_INT_ENA_S 6
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#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
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#define I2S_I2S_TX_REMPTY_INT_ENA_S 5
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#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
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#define I2S_I2S_TX_WFULL_INT_ENA_S 4
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#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
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#define I2S_I2S_RX_REMPTY_INT_ENA_S 3
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#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
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#define I2S_I2S_RX_WFULL_INT_ENA_S 2
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#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
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#define I2S_I2S_TX_PUT_DATA_INT_ENA_S 1
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#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
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#define I2S_I2S_RX_TAKE_DATA_INT_ENA_S 0
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#define I2SINT_CLR (DR_REG_I2S_BASE + 0x0018)
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#define I2S_I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16))
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#define I2S_I2S_OUT_TOTAL_EOF_INT_CLR_S 16
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#define I2S_I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15))
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#define I2S_I2S_IN_DSCR_EMPTY_INT_CLR_S 15
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#define I2S_I2S_OUT_DSCR_ERR_INT_CLR (BIT(14))
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#define I2S_I2S_OUT_DSCR_ERR_INT_CLR_S 14
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#define I2S_I2S_IN_DSCR_ERR_INT_CLR (BIT(13))
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#define I2S_I2S_IN_DSCR_ERR_INT_CLR_S 13
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#define I2S_I2S_OUT_EOF_INT_CLR (BIT(12))
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#define I2S_I2S_OUT_EOF_INT_CLR_S 12
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#define I2S_I2S_OUT_DONE_INT_CLR (BIT(11))
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#define I2S_I2S_OUT_DONE_INT_CLR_S 11
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#define I2S_I2S_IN_ERR_EOF_INT_CLR (BIT(10))
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#define I2S_I2S_IN_ERR_EOF_INT_CLR_S 10
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#define I2S_I2S_IN_SUC_EOF_INT_CLR (BIT(9))
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#define I2S_I2S_IN_SUC_EOF_INT_CLR_S 9
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#define I2S_I2S_IN_DONE_INT_CLR (BIT(8))
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#define I2S_I2S_IN_DONE_INT_CLR_S 8
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#define I2S_I2S_TX_HUNG_INT_CLR (BIT(7))
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#define I2S_I2S_TX_HUNG_INT_CLR_S 7
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#define I2S_I2S_RX_HUNG_INT_CLR (BIT(6))
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#define I2S_I2S_RX_HUNG_INT_CLR_S 6
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#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
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#define I2S_I2S_TX_REMPTY_INT_CLR_S 5
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#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
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#define I2S_I2S_TX_WFULL_INT_CLR_S 4
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#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
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#define I2S_I2S_RX_REMPTY_INT_CLR_S 3
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#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
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#define I2S_I2S_RX_WFULL_INT_CLR_S 2
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#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
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#define I2S_I2S_PUT_DATA_INT_CLR_S 1
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#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
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#define I2S_I2S_TAKE_DATA_INT_CLR_S 0
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#define I2STIMING (DR_REG_I2S_BASE + 0x001c)
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#define I2S_TX_BCK_IN_INV (BIT(24))
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#define I2S_TX_BCK_IN_INV_S 24
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#define I2S_DATA_ENABLE_DELAY 0x00000003
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#define I2S_DATA_ENABLE_DELAY_S 22
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#define I2S_RX_DSYNC_SW (BIT(21))
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#define I2S_RX_DSYNC_SW_S 21
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#define I2S_TX_DSYNC_SW (BIT(20))
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#define I2S_TX_DSYNC_SW_S 20
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#define I2S_RX_BCK_OUT_DELAY 0x00000003
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#define I2S_RX_BCK_OUT_DELAY_S 18
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#define I2S_RX_WS_OUT_DELAY 0x00000003
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#define I2S_RX_WS_OUT_DELAY_S 16
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#define I2S_TX_SD_OUT_DELAY 0x00000003
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#define I2S_TX_SD_OUT_DELAY_S 14
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#define I2S_TX_WS_OUT_DELAY 0x00000003
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#define I2S_TX_WS_OUT_DELAY_S 12
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#define I2S_TX_BCK_OUT_DELAY 0x00000003
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#define I2S_TX_BCK_OUT_DELAY_S 10
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#define I2S_RX_SD_IN_DELAY 0x00000003
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#define I2S_RX_SD_IN_DELAY_S 8
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#define I2S_RX_WS_IN_DELAY 0x00000003
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#define I2S_RX_WS_IN_DELAY_S 6
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#define I2S_RX_BCK_IN_DELAY 0x00000003
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#define I2S_RX_BCK_IN_DELAY_S 4
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#define I2S_TX_WS_IN_DELAY 0x00000003
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#define I2S_TX_WS_IN_DELAY_S 2
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#define I2S_TX_BCK_IN_DELAY 0x00000003
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#define I2S_TX_BCK_IN_DELAY_S 0
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#define I2S_FIFO_CONF (DR_REG_I2S_BASE + 0x0020)
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#define I2S_I2S_RX_FIFO_MOD_FORCE_EN (BIT(20))
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#define I2S_I2S_RX_FIFO_MOD_FORCE_EN_S 20
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#define I2S_I2S_TX_FIFO_MOD_FORCE_EN (BIT(19))
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#define I2S_I2S_TX_FIFO_MOD_FORCE_EN_S 19
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#define I2S_I2S_RX_FIFO_MOD 0x00000007
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#define I2S_I2S_RX_FIFO_MOD_S 16
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#define I2S_I2S_TX_FIFO_MOD 0x00000007
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#define I2S_I2S_TX_FIFO_MOD_S 13
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#define I2S_I2S_DSCR_EN (BIT(12))
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#define I2S_I2S_DSCR_EN_S 12
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#define I2S_I2S_TX_DATA_NUM 0x0000003F
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#define I2S_I2S_TX_DATA_NUM_S 6
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#define I2S_I2S_RX_DATA_NUM 0x0000003F
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#define I2S_I2S_RX_DATA_NUM_S 0
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#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
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#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
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#define I2S_I2S_RX_EOF_NUM_S 0
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#define I2SCONF_SIGLE_DATA (DR_REG_I2S_BASE + 0x0028)
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#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
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#define I2S_I2S_SIGLE_DATA_S 0
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#define I2SCONF_CHAN (DR_REG_I2S_BASE + 0x002c)
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#define I2S_RX_CHAN_MOD 0x00000003
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#define I2S_RX_CHAN_MOD_S 3
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#define I2S_TX_CHAN_MOD 0x00000007
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#define I2S_TX_CHAN_MOD_S 0
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#define I2SOUT_LINK (DR_REG_I2S_BASE + 0x0030)
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#define I2S_OUTLINK_PARK (BIT(31))
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#define I2S_OUTLINK_PARK_S 31
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#define I2S_I2S_OUTLINK_RESTART (BIT(30))
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#define I2S_I2S_OUTLINK_RESTART_S 30
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#define I2S_I2S_OUTLINK_START (BIT(29))
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#define I2S_I2S_OUTLINK_START_S 29
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#define I2S_I2S_OUTLINK_STOP (BIT(28))
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#define I2S_I2S_OUTLINK_STOP_S 28
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#define I2S_I2S_OUTLINK_ADDR 0x000FFFFF
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#define I2S_I2S_OUTLINK_ADDR_S 0
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#define I2SIN_LINK (DR_REG_I2S_BASE + 0x0034)
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#define I2S_INLINK_PARK (BIT(31))
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#define I2S_INLINK_PARK_S 31
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#define I2S_I2S_INLINK_RESTART (BIT(30))
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#define I2S_I2S_INLINK_RESTART_S 30
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#define I2S_I2S_INLINK_START (BIT(29))
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#define I2S_I2S_INLINK_START_S 29
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#define I2S_I2S_INLINK_STOP (BIT(28))
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#define I2S_I2S_INLINK_STOP_S 28
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#define I2S_I2S_INLINK_ADDR 0x000FFFFF
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#define I2S_I2S_INLINK_ADDR_S 0
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#define I2S_OUT_EOF_DES_ADDR (DR_REG_I2S_BASE + 0x0038)
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#define I2S_I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF
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#define I2S_I2S_OUT_EOF_DES_ADDR_S 0
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#define I2S_IN_EOF_DES_ADDR (DR_REG_I2S_BASE + 0x003c)
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#define I2S_I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
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#define I2S_I2S_IN_SUC_EOF_DES_ADDR_S 0
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#define I2S_OUT_EOF_BFR_DES_ADDR (DR_REG_I2S_BASE + 0x0040)
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#define I2S_I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
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#define I2S_I2S_OUT_EOF_BFR_DES_ADDR_S 0
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#define I2S_AHB_TEST (DR_REG_I2S_BASE + 0x0044)
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#define I2S_I2S_AHB_TESTADDR 0x00000003
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#define I2S_I2S_AHB_TESTADDR_S 4
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#define I2S_I2S_AHB_TESTMODE 0x00000007
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#define I2S_I2S_AHB_TESTMODE_S 0
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#define I2S_INLINK_DSCR (DR_REG_I2S_BASE + 0x0048)
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#define I2S_I2S_INLINK_DSCR 0xFFFFFFFF
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#define I2S_I2S_INLINK_DSCR_S 0
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#define I2S_INLINK_DSCR_BF0 (DR_REG_I2S_BASE + 0x004C)
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#define I2S_I2S_INLINK_DSCR_BF0 0xFFFFFFFF
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#define I2S_I2S_INLINK_DSCR_BF0_S 0
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#define I2S_INLINK_DSCR_BF1 (DR_REG_I2S_BASE + 0x0050)
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#define I2S_I2S_INLINK_DSCR_BF1 0xFFFFFFFF
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#define I2S_I2S_INLINK_DSCR_BF1_S 0
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#define I2S_OUTLINK_DSCR (DR_REG_I2S_BASE + 0x0054)
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#define I2S_I2S_OUTLINK_DSCR 0xFFFFFFFF
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#define I2S_I2S_OUTLINK_DSCR_S 0
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#define I2S_OUTLINK_DSCR_BF0 (DR_REG_I2S_BASE + 0x0058)
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#define I2S_I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF
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#define I2S_I2S_OUTLINK_DSCR_BF0_S 0
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#define I2S_OUTLINK_DSCR_BF1 (DR_REG_I2S_BASE + 0x005C)
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#define I2S_I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF
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#define I2S_I2S_OUTLINK_DSCR_BF1_S 0
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#define I2S_LC_CONF (DR_REG_I2S_BASE + 0x0060)
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#define I2S_I2S_MEM_TRANS_EN (BIT(13))
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#define I2S_I2S_MEM_TRANS_EN_S 13
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#define I2S_I2S_CHECK_OWNER (BIT(12))
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#define I2S_I2S_CHECK_OWNER_S 12
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#define I2S_I2S_OUT_DATA_BURST_EN (BIT(11))
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#define I2S_I2S_OUT_DATA_BURST_EN_S 11
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#define I2S_I2S_INDSCR_BURST_EN (BIT(10))
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#define I2S_I2S_INDSCR_BURST_EN_S 10
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#define I2S_I2S_OUTDSCR_BURST_EN (BIT(9))
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#define I2S_I2S_OUTDSCR_BURST_EN_S 9
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#define I2S_I2S_OUT_EOF_MODE (BIT(8))
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#define I2S_I2S_OUT_EOF_MODE_S 8
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#define I2S_I2S_OUT_NO_RESTART_CLR (BIT(7))
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#define I2S_I2S_OUT_NO_RESTART_CLR_S 7
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#define I2S_I2S_OUT_AUTO_WRBACK (BIT(6))
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#define I2S_I2S_OUT_AUTO_WRBACK_S 6
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#define I2S_I2S_IN_LOOP_TEST (BIT(5))
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#define I2S_I2S_IN_LOOP_TEST_S 5
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#define I2S_I2S_OUT_LOOP_TEST (BIT(4))
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#define I2S_I2S_OUT_LOOP_TEST_S 4
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#define I2S_I2S_AHBM_RST (BIT(3))
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#define I2S_I2S_AHBM_RST_S 3
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#define I2S_I2S_AHBM_FIFO_RST (BIT(2))
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#define I2S_I2S_AHBM_FIFO_RST_S 2
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#define I2S_I2S_OUT_RST (BIT(1))
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#define I2S_I2S_OUT_RST_S 1
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#define I2S_I2S_IN_RST (BIT(0))
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#define I2S_I2S_IN_RST_S 0
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#define I2S_OUTFIFO_PUSH (DR_REG_I2S_BASE + 0x0064)
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#define I2S_I2S_OUTFIFO_PUSH (BIT(16))
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#define I2S_I2S_OUTFIFO_PUSH_S 16
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#define I2S_I2S_OUTFIFO_WDATA 0x000001FF
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#define I2S_I2S_OUTFIFO_WDATA_S 0
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#define I2S_INFIFO_POP (DR_REG_I2S_BASE + 0x0068)
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#define I2S_I2S_INFIFO_POP (BIT(16))
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#define I2S_I2S_INFIFO_POP_S 16
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#define I2S_I2S_INFIFO_RDATA 0x00000FFF
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#define I2S_I2S_INFIFO_RDATA_S 0
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#define I2S_LC_STATE0 (DR_REG_I2S_BASE + 0x006C)
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#define I2S_I2S_LC_STATE0 0xFFFFFFFF
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#define I2S_I2S_LC_STATE0_S 0
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#define I2S_LC_STATE1 (DR_REG_I2S_BASE + 0x0070)
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#define I2S_I2S_LC_STATE1 0xFFFFFFFF
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#define I2S_I2S_LC_STATE1_S 0
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#define I2S_LC_HUNG_CONF (DR_REG_I2S_BASE + 0x0074)
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#define I2S_I2S_LC_FIFO_TIMEOUT_ENA (BIT(11))
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#define I2S_I2S_LC_FIFO_TIMEOUT_ENA_S 11
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#define I2S_I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
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#define I2S_I2S_LC_FIFO_TIMEOUT_SHIFT_S 8
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#define I2S_I2S_LC_FIFO_TIMEOUT 0x000000FF
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#define I2S_I2S_LC_FIFO_TIMEOUT_S 0
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#define I2S_CVSD_CONF0 (DR_REG_I2S_BASE + 0x0080)
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#define I2S_I2S_CVSD_Y_MIN 0x0000FFFF
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#define I2S_I2S_CVSD_Y_MIN_S 16
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#define I2S_I2S_CVSD_Y_MAX 0x0000FFFF
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#define I2S_I2S_CVSD_Y_MAX_S 0
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#define I2S_CVSD_CONF1 (DR_REG_I2S_BASE + 0x0084)
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#define I2S_I2S_CVSD_SIGMA_MIN 0x0000FFFF
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#define I2S_I2S_CVSD_SIGMA_MIN_S 16
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#define I2S_I2S_CVSD_SIGMA_MAX 0x0000FFFF
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#define I2S_I2S_CVSD_SIGMA_MAX_S 0
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#define I2S_CVSD_CONF2 (DR_REG_I2S_BASE + 0x0088)
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#define I2S_I2S_CVSD_H 0x00000007
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#define I2S_I2S_CVSD_H_S 16
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#define I2S_I2S_CVSD_BETA 0x000003FF
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#define I2S_I2S_CVSD_BETA_S 6
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#define I2S_I2S_CVSD_J 0x00000007
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#define I2S_I2S_CVSD_J_S 3
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#define I2S_I2S_CVSD_K 0x00000007
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#define I2S_I2S_CVSD_K_S 0
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#define I2S_PLC_CONF0 (DR_REG_I2S_BASE + 0x008C)
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#define I2S_I2S_N_MIN_ERR 0x00000007
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#define I2S_I2S_N_MIN_ERR_S 25
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#define I2S_I2S_PACK_LEN_8K 0x0000001F
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#define I2S_I2S_PACK_LEN_8K_S 20
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#define I2S_I2S_MAX_SLIDE_SAMPLE 0x000000FF
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#define I2S_I2S_MAX_SLIDE_SAMPLE_S 12
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#define I2S_I2S_SHIFT_RATE 0x00000007
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#define I2S_I2S_SHIFT_RATE_S 9
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#define I2S_I2S_N_ERR_SEG 0x00000007
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#define I2S_I2S_N_ERR_SEG_S 6
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#define I2S_I2S_GOOD_PACK_MAX 0x0000003F
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#define I2S_I2S_GOOD_PACK_MAX_S 0
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#define I2S_PLC_CONF1 (DR_REG_I2S_BASE + 0x0090)
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#define I2S_I2S_SLIDE_WIN_LEN 0x000000FF
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#define I2S_I2S_SLIDE_WIN_LEN_S 24
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#define I2S_I2S_BAD_OLA_WIN2_PARA 0x000000FF
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#define I2S_I2S_BAD_OLA_WIN2_PARA_S 16
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#define I2S_I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F
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#define I2S_I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12
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#define I2S_I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F
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#define I2S_I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8
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#define I2S_I2S_BAD_CEF_ATTEN_PARA 0x000000FF
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#define I2S_I2S_BAD_CEF_ATTEN_PARA_S 0
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#define I2S_PLC_CONF2 (DR_REG_I2S_BASE + 0x0094)
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#define I2S_I2S_MIN_PERIOD 0x0000001F
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#define I2S_I2S_MIN_PERIOD_S 2
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#define I2S_I2S_CVSD_SEG_MOD 0x00000003
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#define I2S_I2S_CVSD_SEG_MOD_S 0
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#define I2S_ESCO_CONF0 (DR_REG_I2S_BASE + 0x0098)
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#define I2S_I2S_PLC2DMA_EN (BIT(12))
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#define I2S_I2S_PLC2DMA_EN_S 12
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#define I2S_I2S_PLC_EN (BIT(11))
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#define I2S_I2S_PLC_EN_S 11
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#define I2S_I2S_CVSD_DEC_RESET (BIT(10))
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#define I2S_I2S_CVSD_DEC_RESET_S 10
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#define I2S_I2S_CVSD_DEC_START (BIT(9))
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#define I2S_I2S_CVSD_DEC_START_S 9
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#define I2S_I2S_ESCO_CVSD_INF_EN (BIT(8))
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#define I2S_I2S_ESCO_CVSD_INF_EN_S 8
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#define I2S_I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F
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#define I2S_I2S_ESCO_CVSD_PACK_LEN_8K_S 3
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#define I2S_I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2))
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#define I2S_I2S_ESCO_CVSD_DEC_PACK_ERR_S 2
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#define I2S_I2S_ESCO_CHAN_MOD (BIT(1))
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#define I2S_I2S_ESCO_CHAN_MOD_S 1
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#define I2S_I2S_ESCO_EN (BIT(0))
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#define I2S_I2S_ESCO_EN_S 0
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#define I2S_SCO_CONF0 (DR_REG_I2S_BASE + 0x009c)
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#define I2S_I2S_CVSD_ENC_RESET (BIT(3))
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#define I2S_I2S_CVSD_ENC_RESET_S 3
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#define I2S_I2S_CVSD_ENC_START (BIT(2))
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#define I2S_I2S_CVSD_ENC_START_S 2
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#define I2S_I2S_SCO_NO_I2S_EN (BIT(1))
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#define I2S_I2S_SCO_NO_I2S_EN_S 1
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#define I2S_I2S_SCO_WITH_I2S_EN (BIT(0))
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#define I2S_I2S_SCO_WITH_I2S_EN_S 0
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#define I2SCONF1 (DR_REG_I2S_BASE + 0x00a0)
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#define I2S_I2S_TX_ZEROS_RM_EN (BIT(9))
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#define I2S_I2S_TX_ZEROS_RM_EN_S 9
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#define I2S_I2S_TX_STOP_EN (BIT(8))
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#define I2S_I2S_TX_STOP_EN_S 8
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#define I2S_RX_PCM_BYPASS (BIT(7))
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#define I2S_RX_PCM_BYPASS_S 7
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#define I2S_RX_PCM_CONF 0x00000007
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#define I2S_RX_PCM_CONF_S 4
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#define I2S_TX_PCM_BYPASS (BIT(3))
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#define I2S_TX_PCM_BYPASS_S 3
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#define I2S_TX_PCM_CONF 0x00000007
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#define I2S_TX_PCM_CONF_S 0
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#define I2S_PD_CONF (DR_REG_I2S_BASE + 0x00a4)
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#define I2S_PLC_MEM_FORCE_PU (BIT(3))
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#define I2S_PLC_MEM_FORCE_PU_S 3
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#define I2S_PLC_MEM_FORCE_PD (BIT(2))
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#define I2S_PLC_MEM_FORCE_PD_S 2
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#define I2S_I2S_FIFO_FORCE_PU (BIT(1))
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#define I2S_I2S_FIFO_FORCE_PU_S 1
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#define I2S_I2S_FIFO_FORCE_PD (BIT(0))
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#define I2S_I2S_FIFO_FORCE_PD_S 0
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#define I2SCONF2 (DR_REG_I2S_BASE + 0x00a8)
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#define I2S_INTER_VALID_EN (BIT(7))
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#define I2S_INTER_VALID_EN_S 7
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#define I2S_EXT_ADC_START_EN (BIT(6))
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#define I2S_EXT_ADC_START_EN_S 6
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#define I2S_LCD_EN (BIT(5))
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#define I2S_LCD_EN_S 5
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#define I2S_DATA_ENABLE (BIT(4))
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#define I2S_DATA_ENABLE_S 4
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#define I2S_DATA_ENABLE_TEST_EN (BIT(3))
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#define I2S_DATA_ENABLE_TEST_EN_S 3
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#define I2S_LCD_TX_SDX2_EN (BIT(2))
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#define I2S_LCD_TX_SDX2_EN_S 2
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#define I2S_LCD_TX_WRX2_EN (BIT(1))
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#define I2S_LCD_TX_WRX2_EN_S 1
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#define I2S_CAMERA_EN (BIT(0))
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#define I2S_CAMERA_EN_S 0
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#define I2S_CLKM_CONF (DR_REG_I2S_BASE + 0x00ac)
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#define I2S_CLKA_ENA (BIT(21))
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#define I2S_CLKA_ENA_S 21
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#define I2S_CLK_EN (BIT(20))
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#define I2S_CLK_EN_S 20
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#define I2S_CLKM_DIV_A 0x0000003F
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#define I2S_CLKM_DIV_A_S 14
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#define I2S_CLKM_DIV_B 0x0000003F
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#define I2S_CLKM_DIV_B_S 8
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#define I2S_CLKM_DIV_NUM 0x000000FF
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#define I2S_CLKM_DIV_NUM_S 0
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#define I2S_SAMPLE_RATE_CONF (DR_REG_I2S_BASE + 0x00b0)
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#define I2S_RX_BITS_MOD 0x0000003F
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#define I2S_RX_BITS_MOD_S 18
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#define I2S_TX_BITS_MOD 0x0000003F
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#define I2S_TX_BITS_MOD_S 12
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#define I2S_RX_BCK_DIV_NUM 0x0000003F
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#define I2S_RX_BCK_DIV_NUM_S 6
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#define I2S_TX_BCK_DIV_NUM 0x0000003F
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#define I2S_TX_BCK_DIV_NUM_S 0
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#define I2S_PDM_CONF (DR_REG_I2S_BASE + 0x00b4)
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#define I2S_TX_PDM_HP_BYPASS (BIT(25))
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#define I2S_TX_PDM_HP_BYPASS_S 25
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#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24))
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#define I2S_RX_PDM_SINC_DSR_16_EN_S 24
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#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003
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#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22
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#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003
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#define I2S_TX_PDM_SINC_IN_SHIFT_S 20
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#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003
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#define I2S_TX_PDM_LP_IN_SHIFT_S 18
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#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003
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#define I2S_TX_PDM_HP_IN_SHIFT_S 16
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#define I2S_TX_PDM_PRESCALE 0x000000FF
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#define I2S_TX_PDM_PRESCALE_S 8
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#define I2S_TX_PDM_SINC_OSR2 0x0000000F
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#define I2S_TX_PDM_SINC_OSR2_S 4
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#define I2S_PDM2PCM_CONV_EN (BIT(3))
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#define I2S_PDM2PCM_CONV_EN_S 3
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#define I2S_PCM2PDM_CONV_EN (BIT(2))
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#define I2S_PCM2PDM_CONV_EN_S 2
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#define I2S_RX_PDM_EN (BIT(1))
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#define I2S_RX_PDM_EN_S 1
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#define I2S_TX_PDM_EN (BIT(0))
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#define I2S_TX_PDM_EN_S 0
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#define I2S_PDM_FREQ_CONF (DR_REG_I2S_BASE + 0x00b8)
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#define I2S_TX_PDM_FP 0x000003FF
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#define I2S_TX_PDM_FP_S 10
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#define I2S_TX_PDM_FS 0x000003FF
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#define I2S_TX_PDM_FS_S 0
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#define I2S_STATE (DR_REG_I2S_BASE + 0x00bc)
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#define I2S_I2S_RX_FIFO_RESET_BACK (BIT(2))
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#define I2S_I2S_RX_FIFO_RESET_BACK_S 2
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#define I2S_I2S_TX_FIFO_RESET_BACK (BIT(1))
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#define I2S_I2S_TX_FIFO_RESET_BACK_S 1
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#define I2S_I2S_TX_IDLE (BIT(0))
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#define I2S_I2S_TX_IDLE_S 0
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#define I2S_DATE (DR_REG_I2S_BASE + 0x00fc)
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#define I2S_I2SDATE 0xFFFFFFFF
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#define I2S_I2SDATE_S 0
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#endif /* _SOC_I2S_REG_H_ */
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