351 lines
12 KiB
C
351 lines
12 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
|
//
|
|
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
// you may not use this file except in compliance with the License.
|
|
// You may obtain a copy of the License at
|
|
|
|
// http://www.apache.org/licenses/LICENSE-2.0
|
|
//
|
|
// Unless required by applicable law or agreed to in writing, software
|
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
// See the License for the specific language governing permissions and
|
|
// limitations under the License.
|
|
#ifndef _SOC_UHCI0_REG_H_
|
|
#define _SOC_UHCI0_REG_H_
|
|
|
|
#include "soc.h"
|
|
|
|
#define UHCI0_CONF0 ( DR_REG_UHCI0_BASE + 0x0)
|
|
#define UHCI0_UART_RX_BRK_EOF_EN (BIT(22))
|
|
#define UHCI0_CLK_EN (BIT(21))
|
|
#define UHCI0_ENCODE_CRC_EN (BIT(20))
|
|
#define UHCI0_LEN_EOF_EN (BIT(19))
|
|
#define UHCI0_UART_IDLE_EOF_EN (BIT(18))
|
|
#define UHCI0_CRC_REC_EN (BIT(17))
|
|
#define UHCI0_HEAD_EN (BIT(16))
|
|
#define UHCI0_SEPER_EN (BIT(15))
|
|
#define UHCI0_MEM_TRANS_EN (BIT(14))
|
|
#define UHCI0_RX_DATA_BURST_EN (BIT(13))
|
|
#define UHCI0_TXDSCR_BURST_EN (BIT(12))
|
|
#define UHCI0_RXDSCR_BURST_EN (BIT(11))
|
|
#define UHCI0_UART1_CE (BIT(10))
|
|
#define UHCI0_UART0_CE (BIT(9))
|
|
#define UHCI0_TO_EOF_MODE (BIT(8))
|
|
#define UHCI0_RX_NO_RESTART_CLR (BIT(7))
|
|
#define UHCI0_RX_AUTO_WRBACK (BIT(6))
|
|
#define UHCI0_RX_LOOP_TEST (BIT(5))
|
|
#define UHCI0_TX_LOOP_TEST (BIT(4))
|
|
#define UHCI0_AHBM_RST (BIT(3))
|
|
#define UHCI0_AHBM_FIFO_RST (BIT(2))
|
|
#define UHCI0_RX_RST (BIT(1))
|
|
#define UHCI0_TX_RST (BIT(0))
|
|
|
|
#define UHCI0_INT_RAW ( DR_REG_UHCI0_BASE + 0x4)
|
|
#define UHCI0_UHCI_SEND_A_Q_INT_RAW (BIT(15))
|
|
#define UHCI0_UHCI_SEND_S_Q_INT_RAW (BIT(14))
|
|
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_RAW (BIT(13))
|
|
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_RAW (BIT(12))
|
|
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_RAW (BIT(11))
|
|
#define UHCI0_UHCI_RX_DSCR_ERR_INT_RAW (BIT(10))
|
|
#define UHCI0_UHCI_TX_DSCR_ERR_INT_RAW (BIT(9))
|
|
#define UHCI0_UHCI_TO_EOF_INT_RAW (BIT(8))
|
|
#define UHCI0_UHCI_RX_DONE_INT_RAW (BIT(7))
|
|
#define UHCI0_UHCI_FROM_ERR_EOF_INT_RAW (BIT(6))
|
|
#define UHCI0_UHCI_FROM_SUC_EOF_INT_RAW (BIT(5))
|
|
#define UHCI0_UHCI_TX_DONE_INT_RAW (BIT(4))
|
|
#define UHCI0_UHCI_TX_HUNG_INT_RAW (BIT(3))
|
|
#define UHCI0_UHCI_RX_HUNG_INT_RAW (BIT(2))
|
|
#define UHCI0_UHCI_TX_START_INT_RAW (BIT(1))
|
|
#define UHCI0_UHCI_RX_START_INT_RAW (BIT(0))
|
|
|
|
#define UHCI0_INT_ST ( DR_REG_UHCI0_BASE + 0x8)
|
|
#define UHCI0_UHCI_SEND_A_Q_INT_ST (BIT(15))
|
|
#define UHCI0_UHCI_SEND_S_Q_INT_ST (BIT(14))
|
|
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ST (BIT(13))
|
|
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ST (BIT(12))
|
|
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ST (BIT(11))
|
|
#define UHCI0_UHCI_RX_DSCR_ERR_INT_ST (BIT(10))
|
|
#define UHCI0_UHCI_TX_DSCR_ERR_INT_ST (BIT(9))
|
|
#define UHCI0_UHCI_TO_EOF_INT_ST (BIT(8))
|
|
#define UHCI0_UHCI_RX_DONE_INT_ST (BIT(7))
|
|
#define UHCI0_UHCI_FROM_ERR_EOF_INT_ST (BIT(6))
|
|
#define UHCI0_UHCI_FROM_SUC_EOF_INT_ST (BIT(5))
|
|
#define UHCI0_UHCI_TX_DONE_INT_ST (BIT(4))
|
|
#define UHCI0_UHCI_TX_HUNG_INT_ST (BIT(3))
|
|
#define UHCI0_UHCI_RX_HUNG_INT_ST (BIT(2))
|
|
#define UHCI0_UHCI_TX_START_INT_ST (BIT(1))
|
|
#define UHCI0_UHCI_RX_START_INT_ST (BIT(0))
|
|
|
|
#define UHCI0_INT_ENA ( DR_REG_UHCI0_BASE + 0xC)
|
|
#define UHCI0_UHCI_SEND_A_Q_INT_ENA (BIT(15))
|
|
#define UHCI0_UHCI_SEND_S_Q_INT_ENA (BIT(14))
|
|
#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ENA (BIT(13))
|
|
#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ENA (BIT(12))
|
|
#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ENA (BIT(11))
|
|
#define UHCI0_UHCI_RX_DSCR_ERR_INT_ENA (BIT(10))
|
|
#define UHCI0_UHCI_TX_DSCR_ERR_INT_ENA (BIT(9))
|
|
#define UHCI0_UHCI_TO_EOF_INT_ENA (BIT(8))
|
|
#define UHCI0_UHCI_RX_DONE_INT_ENA (BIT(7))
|
|
#define UHCI0_UHCI_FROM_ERR_EOF_INT_ENA (BIT(6))
|
|
#define UHCI0_UHCI_FROM_SUC_EOF_INT_ENA (BIT(5))
|
|
#define UHCI0_UHCI_TX_DONE_INT_ENA (BIT(4))
|
|
#define UHCI0_UHCI_TX_HUNG_INT_ENA (BIT(3))
|
|
#define UHCI0_UHCI_RX_HUNG_INT_ENA (BIT(2))
|
|
#define UHCI0_UHCI_TX_START_INT_ENA (BIT(1))
|
|
#define UHCI0_UHCI_RX_START_INT_ENA (BIT(0))
|
|
|
|
#define UHCI0_INT_CLR ( DR_REG_UHCI0_BASE + 0x10)
|
|
#define UHCI0_SEND_A_REG_Q_INT_CLR (BIT(15))
|
|
#define UHCI0_SEND_S_REG_Q_INT_CLR (BIT(14))
|
|
#define UHCI0_TO_TOTAL_EOF_INT_CLR (BIT(13))
|
|
#define UHCI0_RXLINK_EOF_ERR_INT_CLR (BIT(12))
|
|
#define UHCI0_TX_DSCR_EMPTY_INT_CLR (BIT(11))
|
|
#define UHCI0_RX_DSCR_ERR_INT_CLR (BIT(10))
|
|
#define UHCI0_TX_DSCR_ERR_INT_CLR (BIT(9))
|
|
#define UHCI0_TO_EOF_INT_CLR (BIT(8))
|
|
#define UHCI0_RX_DONE_INT_CLR (BIT(7))
|
|
#define UHCI0_FROM_ERR_EOF_INT_CLR (BIT(6))
|
|
#define UHCI0_FROM_SUC_EOF_INT_CLR (BIT(5))
|
|
#define UHCI0_TX_DONE_INT_CLR (BIT(4))
|
|
#define UHCI0_TX_HUNG_INT_CLR (BIT(3))
|
|
#define UHCI0_RX_HUNG_INT_CLR (BIT(2))
|
|
#define UHCI0_TX_START_INT_CLR (BIT(1))
|
|
#define UHCI0_RX_START_INT_CLR (BIT(0))
|
|
|
|
#define UHCI0_RX_STATUS ( DR_REG_UHCI0_BASE + 0x14)
|
|
#define UHCI0_RX_EMPTY (BIT(1))
|
|
#define UHCI0_RX_FULL (BIT(0))
|
|
|
|
#define UHCI0_RXFIFO_PUSH ( DR_REG_UHCI0_BASE + 0x18)
|
|
#define UHCI0_RXFIFO_PUSH_EN (BIT(16))
|
|
#define UHCI0_RXFIFO_WDATA 0x000001FF
|
|
#define UHCI0_RXFIFO_WDATA_S 0
|
|
|
|
#define UHCI0_TX_STATUS ( DR_REG_UHCI0_BASE + 0x1C)
|
|
#define UHCI0_UHCI_RX_ERR_CAUSE 0x00000007
|
|
#define UHCI0_UHCI_RX_ERR_CAUSE_S 4
|
|
#define UHCI0_TX_EMPTY (BIT(1))
|
|
#define UHCI0_TX_FULL (BIT(0))
|
|
|
|
#define UHCI0_TX_POP ( DR_REG_UHCI0_BASE + 0x20)
|
|
#define UHCI0_TXFIFO_POP (BIT(16))
|
|
#define UHCI0_TXFIFO_RDATA 0x00000FFF
|
|
#define UHCI0_TXFIFO_RDATA_S 0
|
|
|
|
#define UHCI0_RX_LINK ( DR_REG_UHCI0_BASE + 0x24)
|
|
#define UHCI0_UHCI_RXLINK_PARK (BIT(31))
|
|
#define UHCI0_RXLINK_RESTART (BIT(30))
|
|
#define UHCI0_RXLINK_START (BIT(29))
|
|
#define UHCI0_RXLINK_STOP (BIT(28))
|
|
#define UHCI0_RXLINK_ADDR 0x000FFFFF
|
|
#define UHCI0_RXLINK_ADDR_S 0
|
|
|
|
#define UHCI0_TX_LINK ( DR_REG_UHCI0_BASE + 0x28)
|
|
#define UHCI0_UHCI_TXLINK_PARK (BIT(31))
|
|
#define UHCI0_TXLINK_RESTART (BIT(30))
|
|
#define UHCI0_TXLINK_START (BIT(29))
|
|
#define UHCI0_TXLINK_STOP (BIT(28))
|
|
#define UHCI0_TXLINK_AUTO_RET (BIT(20))
|
|
#define UHCI0_TXLINK_ADDR 0x000FFFFF
|
|
#define UHCI0_TXLINK_ADDR_S 0
|
|
|
|
#define UHCI0_CONF1 ( DR_REG_UHCI0_BASE + 0x2C)
|
|
#define UHCI0_SW_START (BIT(8))
|
|
#define UHCI0_WAIT_SW_START (BIT(7))
|
|
#define UHCI0_CHECK_OWNER (BIT(6))
|
|
#define UHCI0_TX_ACK_NUM_RE (BIT(5))
|
|
#define UHCI0_TX_CHECK_SUM_RE (BIT(4))
|
|
#define UHCI0_SAVE_HEAD (BIT(3))
|
|
#define UHCI0_CRC_DISABLE (BIT(2))
|
|
#define UHCI0_CHECK_SEQ_EN (BIT(1))
|
|
#define UHCI0_CHECK_SUM_EN (BIT(0))
|
|
|
|
#define UHCI0_STATE0 ( DR_REG_UHCI0_BASE + 0x30)
|
|
#define UHCI0_UHCI_STATE0 0xFFFFFFFF
|
|
#define UHCI0_UHCI_STATE0_S 0
|
|
|
|
#define UHCI0_STATE1 ( DR_REG_UHCI0_BASE + 0x34)
|
|
#define UHCI0_UHCI_STATE1 0xFFFFFFFF
|
|
#define UHCI0_UHCI_STATE1_S 0
|
|
|
|
#define UHCI0_RX_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x38)
|
|
#define UHCI0_TO_EOF_DES_ADDR 0xFFFFFFFF
|
|
#define UHCI0_TO_EOF_DES_ADDR_S 0
|
|
|
|
#define UHCI0_TX_SUC_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x3C)
|
|
#define UHCI0_FROM_SUC_EOF_DES_ADDR 0xFFFFFFFF
|
|
#define UHCI0_FROM_SUC_EOF_DES_ADDR_S 0
|
|
|
|
#define UHCI0_TX_ERR_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x40)
|
|
#define UHCI0_FROM_ERR_EOF_DES_ADDR 0xFFFFFFFF
|
|
#define UHCI0_FROM_ERR_EOF_DES_ADDR_S 0
|
|
|
|
#define UHCI0_RX_EOF_BFR_DES_ADDR ( DR_REG_UHCI0_BASE + 0x44)
|
|
#define UHCI0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF
|
|
#define UHCI0_TO_EOF_BFR_DES_ADDR_S 0
|
|
|
|
#define UHCI0_AHB_TEST ( DR_REG_UHCI0_BASE + 0x48)
|
|
#define UHCI0_AHB_TESTADDR 0x00000003
|
|
#define UHCI0_AHB_TESTADDR_S 4
|
|
#define UHCI0_AHB_TESTMODE 0x00000007
|
|
#define UHCI0_AHB_TESTMODE_S 0
|
|
|
|
#define UHCI0_TX_DSCR ( DR_REG_UHCI0_BASE + 0x4C)
|
|
#define UHCI0_TXLINK_DSCR 0xFFFFFFFF
|
|
#define UHCI0_TXLINK_DSCR_S 0
|
|
|
|
#define UHCI0_TX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x50)
|
|
#define UHCI0_TXLINK_DSCR_BF0 0xFFFFFFFF
|
|
#define UHCI0_TXLINK_DSCR_BF0_S 0
|
|
|
|
#define UHCI0_TX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x54)
|
|
#define UHCI0_TXLINK_DSCR_BF1 0xFFFFFFFF
|
|
#define UHCI0_TXLINK_DSCR_BF1_S 0
|
|
|
|
#define UHCI0_RX_DSCR ( DR_REG_UHCI0_BASE + 0x58)
|
|
#define UHCI0_RXLINK_DSCR 0xFFFFFFFF
|
|
#define UHCI0_RXLINK_DSCR_S 0
|
|
|
|
#define UHCI0_RX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x5C)
|
|
#define UHCI0_RXLINK_DSCR_BF0 0xFFFFFFFF
|
|
#define UHCI0_RXLINK_DSCR_BF0_S 0
|
|
|
|
#define UHCI0_RX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x60)
|
|
#define UHCI0_RXLINK_DSCR_BF1 0xFFFFFFFF
|
|
#define UHCI0_RXLINK_DSCR_BF1_S 0
|
|
|
|
#define UHCI0_ESCAPE_CONF ( DR_REG_UHCI0_BASE + 0x64)
|
|
#define UHCI0_RX_13_ESC_EN (BIT(7))
|
|
#define UHCI0_RX_11_ESC_EN (BIT(6))
|
|
#define UHCI0_RX_DB_ESC_EN (BIT(5))
|
|
#define UHCI0_RX_C0_ESC_EN (BIT(4))
|
|
#define UHCI0_TX_13_ESC_EN (BIT(3))
|
|
#define UHCI0_TX_11_ESC_EN (BIT(2))
|
|
#define UHCI0_TX_DB_ESC_EN (BIT(1))
|
|
#define UHCI0_TX_C0_ESC_EN (BIT(0))
|
|
|
|
#define UHCI0_HUNG_CONF ( DR_REG_UHCI0_BASE + 0x68)
|
|
#define UHCI0_RXFIFO_TIMEOUT_ENA (BIT(23))
|
|
#define UHCI0_RXFIFO_TIMEOUT_SHIFT 0x00000007
|
|
#define UHCI0_RXFIFO_TIMEOUT_SHIFT_S 20
|
|
#define UHCI0_RXFIFO_TIMEOUT 0x000000FF
|
|
#define UHCI0_RXFIFO_TIMEOUT_S 12
|
|
#define UHCI0_TXFIFO_TIMEOUT_ENA (BIT(11))
|
|
#define UHCI0_TXFIFO_TIMEOUT_SHIFT 0x00000007
|
|
#define UHCI0_TXFIFO_TIMEOUT_SHIFT_S 8
|
|
#define UHCI0_TXFIFO_TIMEOUT 0x000000FF
|
|
#define UHCI0_TXFIFO_TIMEOUT_S 0
|
|
|
|
#define UHCI0_ACK_NUM ( DR_REG_UHCI0_BASE + 0x6C)
|
|
|
|
#define UHCI0_RX_HEAD ( DR_REG_UHCI0_BASE + 0x70)
|
|
#define UHCI0_UHCI_RX_HEAD 0xFFFFFFFF
|
|
#define UHCI0_UHCI_RX_HEAD_S 0
|
|
|
|
#define UHCI0_QUICK_SENT ( DR_REG_UHCI0_BASE + 0x74)
|
|
#define UHCI0_ALWAYS_SEND_EN (BIT(7))
|
|
#define UHCI0_ALWAYS_SEND_NUM 0x00000007
|
|
#define UHCI0_ALWAYS_SEND_NUM_S 4
|
|
#define UHCI0_SINGLE_SEND_EN (BIT(3))
|
|
#define UHCI0_SINGLE_SEND_NUM 0x00000007
|
|
#define UHCI0_SINGLE_SEND_NUM_S 0
|
|
|
|
#define UHCI0_REG_Q0_WORD0 ( DR_REG_UHCI0_BASE + 0x78)
|
|
#define UHCI0_SEND_Q0_WORD0 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q0_WORD0_S 0
|
|
|
|
#define UHCI0_REG_Q0_WORD1 ( DR_REG_UHCI0_BASE + 0x7C)
|
|
#define UHCI0_SEND_Q0_WORD1 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q0_WORD1_S 0
|
|
|
|
#define UHCI0_REG_Q1_WORD0 ( DR_REG_UHCI0_BASE + 0x80)
|
|
#define UHCI0_SEND_Q1_WORD0 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q1_WORD0_S 0
|
|
|
|
#define UHCI0_REG_Q1_WORD1 ( DR_REG_UHCI0_BASE + 0x84)
|
|
#define UHCI0_SEND_Q1_WORD1 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q1_WORD1_S 0
|
|
|
|
#define UHCI0_REG_Q2_WORD0 ( DR_REG_UHCI0_BASE + 0x88)
|
|
#define UHCI0_SEND_Q2_WORD0 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q2_WORD0_S 0
|
|
|
|
#define UHCI0_REG_Q2_WORD1 ( DR_REG_UHCI0_BASE + 0x8C)
|
|
#define UHCI0_SEND_Q2_WORD1 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q2_WORD1_S 0
|
|
|
|
#define UHCI0_REG_Q3_WORD0 ( DR_REG_UHCI0_BASE + 0x90)
|
|
#define UHCI0_SEND_Q3_WORD0 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q3_WORD0_S 0
|
|
|
|
#define UHCI0_REG_Q3_WORD1 ( DR_REG_UHCI0_BASE + 0x94)
|
|
#define UHCI0_SEND_Q3_WORD1 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q3_WORD1_S 0
|
|
|
|
#define UHCI0_REG_Q4_WORD0 ( DR_REG_UHCI0_BASE + 0x98)
|
|
#define UHCI0_SEND_Q4_WORD0 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q4_WORD0_S 0
|
|
|
|
#define UHCI0_REG_Q4_WORD1 ( DR_REG_UHCI0_BASE + 0x9C)
|
|
#define UHCI0_SEND_Q4_WORD1 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q4_WORD1_S 0
|
|
|
|
#define UHCI0_REG_Q5_WORD0 ( DR_REG_UHCI0_BASE + 0xA0)
|
|
#define UHCI0_SEND_Q5_WORD0 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q5_WORD0_S 0
|
|
|
|
#define UHCI0_REG_Q5_WORD1 ( DR_REG_UHCI0_BASE + 0xA4)
|
|
#define UHCI0_SEND_Q5_WORD1 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q5_WORD1_S 0
|
|
|
|
#define UHCI0_REG_Q6_WORD0 ( DR_REG_UHCI0_BASE + 0xA8)
|
|
#define UHCI0_SEND_Q6_WORD0 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q6_WORD0_S 0
|
|
|
|
#define UHCI0_REG_Q6_WORD1 ( DR_REG_UHCI0_BASE + 0xAC)
|
|
#define UHCI0_SEND_Q6_WORD1 0xFFFFFFFF
|
|
#define UHCI0_SEND_Q6_WORD1_S 0
|
|
|
|
#define UHCI0_ESC_CONF0 ( DR_REG_UHCI0_BASE + 0xB0)
|
|
#define UHCI0_SEPER_ESC_CHAR1 0x000000FF
|
|
#define UHCI0_SEPER_ESC_CHAR1_S 16
|
|
#define UHCI0_SEPER_ESC_CHAR0 0x000000FF
|
|
#define UHCI0_SEPER_ESC_CHAR0_S 8
|
|
#define UHCI0_SEPER_CHAR 0x000000FF
|
|
#define UHCI0_SEPER_CHAR_S 0
|
|
|
|
#define UHCI0_ESC_CONF1 ( DR_REG_UHCI0_BASE + 0xB4)
|
|
#define UHCI0_ESC_SEQ0_CHAR1 0x000000FF
|
|
#define UHCI0_ESC_SEQ0_CHAR1_S 16
|
|
#define UHCI0_ESC_SEQ0_CHAR0 0x000000FF
|
|
#define UHCI0_ESC_SEQ0_CHAR0_S 8
|
|
#define UHCI0_ESC_SEQ0 0x000000FF
|
|
#define UHCI0_ESC_SEQ0_S 0
|
|
|
|
#define UHCI0_ESC_CONF2 ( DR_REG_UHCI0_BASE + 0xB8)
|
|
#define UHCI0_ESC_SEQ1_CHAR1 0x000000FF
|
|
#define UHCI0_ESC_SEQ1_CHAR1_S 16
|
|
#define UHCI0_ESC_SEQ1_CHAR0 0x000000FF
|
|
#define UHCI0_ESC_SEQ1_CHAR0_S 8
|
|
#define UHCI0_ESC_SEQ1 0x000000FF
|
|
#define UHCI0_ESC_SEQ1_S 0
|
|
|
|
#define UHCI0_ESC_CONF3 ( DR_REG_UHCI0_BASE + 0xBC)
|
|
#define UHCI0_ESC_SEQ2_CHAR1 0x000000FF
|
|
#define UHCI0_ESC_SEQ2_CHAR1_S 16
|
|
#define UHCI0_ESC_SEQ2_CHAR0 0x000000FF
|
|
#define UHCI0_ESC_SEQ2_CHAR0_S 8
|
|
#define UHCI0_ESC_SEQ2 0x000000FF
|
|
#define UHCI0_ESC_SEQ2_S 0
|
|
|
|
#define UHCI0_PKT_THRES ( DR_REG_UHCI0_BASE + 0xC0)
|
|
#define UHCI0_PKT_THRS 0x00001FFF
|
|
#define UHCI0_PKT_THRS_S 0
|
|
|
|
#define UHCI0_DATA ( DR_REG_UHCI0_BASE + 0xFC)
|
|
#define UHCI0_UHCI_DATA 0xFFFFFFFF
|
|
#define UHCI0_UHCI_DATA_S 0
|
|
|
|
#endif /* _SOC_UHCI0_REG_H_ */
|