24011ddd05
1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
289 lines
9.2 KiB
C
289 lines
9.2 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_TIMERS_REG_H_
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#define _SOC_TIMER_REG_H_
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#include "soc.h"
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#define T0CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0000)
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#define TIMERS_T0_EN (BIT(31))
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#define TIMERS_T0_EN_S 31
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#define TIMERS_T0_INCREASE (BIT(30))
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#define TIMERS_T0_INCREASE_S 30
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#define TIMERS_T0_AUTORELOAD (BIT(29))
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#define TIMERS_T0_AUTORELOAD_S 29
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#define TIMERS_T0_DIVIDER 0x0000FFFF
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#define TIMERS_T0_DIVIDER_S 13
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#define TIMERS_T0_EDGE_INT_EN (BIT(12))
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#define TIMERS_T0_EDGE_INT_EN_S 12
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#define TIMERS_T0_LEVEL_INT_EN (BIT(11))
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#define TIMERS_T0_LEVEL_INT_EN_S 11
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#define TIMERS_T0_ALARM_EN (BIT(10))
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#define TIMERS_T0_ALARM_EN_S 10
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#define T0LO(i) (DR_REG_TIMERS_BASE(i) + 0x0004)
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#define TIMERS_T0_LO 0xFFFFFFFF
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#define TIMERS_T0_LO_S 0
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#define T0HI(i) (DR_REG_TIMERS_BASE(i) + 0x0008)
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#define TIMERS_T0_HI 0xFFFFFFFF
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#define TIMERS_T0_HI_S 0
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#define T0UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x000c)
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#define TIMERS_T0_UPDATE 0xFFFFFFFF
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#define TIMERS_T0_UPDATE_S 0
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#define T0ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0010)
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#define TIMERS_T0_ALARM_LO 0xFFFFFFFF
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#define TIMERS_T0_ALARM_LO_S 0
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#define T0ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0014)
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#define TIMERS_T0_ALARM_HI 0xFFFFFFFF
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#define TIMERS_T0_ALARM_HI_S 0
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#define T0LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x0018)
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#define TIMERS_T0_LOAD_LO 0xFFFFFFFF
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#define TIMERS_T0_LOAD_LO_S 0
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#define T0LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x001c)
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#define TIMERS_T0_LOAD_HI 0xFFFFFFFF
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#define TIMERS_T0_LOAD_HI_S 0
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#define T0LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0020)
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#define TIMERS_T0_LOAD 0xFFFFFFFF
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#define TIMERS_T0_LOAD_S 0
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#define T1CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0024)
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#define TIMERS_T1_EN (BIT(31))
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#define TIMERS_T1_EN_S 31
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#define TIMERS_T1_INCREASE (BIT(30))
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#define TIMERS_T1_INCREASE_S 30
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#define TIMERS_T1_AUTORELOAD (BIT(29))
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#define TIMERS_T1_AUTORELOAD_S 29
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#define TIMERS_T1_DIVIDER 0x0000FFFF
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#define TIMERS_T1_DIVIDER_S 13
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#define TIMERS_T1_EDGE_INT_EN (BIT(12))
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#define TIMERS_T1_EDGE_INT_EN_S 12
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#define TIMERS_T1_LEVEL_INT_EN (BIT(11))
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#define TIMERS_T1_LEVEL_INT_EN_S 11
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#define TIMERS_T1_ALARM_EN (BIT(10))
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#define TIMERS_T1_ALARM_EN_S 10
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#define T1LO(i) (DR_REG_TIMERS_BASE(i) + 0x0028)
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#define TIMERS_T1_LO 0xFFFFFFFF
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#define TIMERS_T1_LO_S 0
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#define T1HI(i) (DR_REG_TIMERS_BASE(i) + 0x002c)
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#define TIMERS_T1_HI 0xFFFFFFFF
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#define TIMERS_T1_HI_S 0
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#define T1UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0030)
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#define TIMERS_T1_UPDATE 0xFFFFFFFF
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#define TIMERS_T1_UPDATE_S 0
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#define T1ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0034)
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#define TIMERS_T1_ALARM_LO 0xFFFFFFFF
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#define TIMERS_T1_ALARM_LO_S 0
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#define T1ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0038)
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#define TIMERS_T1_ALARM_HI 0xFFFFFFFF
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#define TIMERS_T1_ALARM_HI_S 0
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#define T1LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x003c)
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#define TIMERS_T1_LOAD_LO 0xFFFFFFFF
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#define TIMERS_T1_LOAD_LO_S 0
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#define T1LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0040)
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#define TIMERS_T1_LOAD_HI 0xFFFFFFFF
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#define TIMERS_T1_LOAD_HI_S 0
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#define T1LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0044)
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#define TIMERS_T1_LOAD 0xFFFFFFFF
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#define TIMERS_T1_LOAD_S 0
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#define WDTCONFIG0(i) (DR_REG_TIMERS_BASE(i) + 0x0048)
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#define TIMERS_WDT_EN (BIT(31))
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#define TIMERS_WDT_EN_S 31
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#define TIMERS_WDT_STG0 0x00000003
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#define TIMERS_WDT_STG0_S 29
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#define TIMERS_WDT_STG1 0x00000003
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#define TIMERS_WDT_STG1_S 27
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#define TIMERS_WDT_STG2 0x00000003
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#define TIMERS_WDT_STG2_S 25
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#define TIMERS_WDT_STG3 0x00000003
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#define TIMERS_WDT_STG3_S 23
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#define TIMERS_WDT_EDGE_INT_EN (BIT(22))
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#define TIMERS_WDT_EDGE_INT_EN_S 22
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#define TIMERS_WDT_LEVEL_INT_EN (BIT(21))
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#define TIMERS_WDT_LEVEL_INT_EN_S 21
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#define TIMERS_WDT_CPU_RESET_LENGTH 0x00000007
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#define TIMERS_WDT_CPU_RESET_LENGTH_S 18
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#define TIMERS_WDT_SYS_RESET_LENGTH 0x00000007
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#define TIMERS_WDT_SYS_RESET_LENGTH_S 15
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#define TIMERS_WDT_FLASHBOOT_MOD_EN (BIT(14))
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#define TIMERS_WDT_FLASHBOOT_MOD_EN_S 14
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#define WDTCONFIG1(i) (DR_REG_TIMERS_BASE(i) + 0x004c)
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#define TIMERS_WDT_CLK_PRESCALE 0x0000FFFF
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#define TIMERS_WDT_CLK_PRESCALE_S 16
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#define WDTCONFIG2(i) (DR_REG_TIMERS_BASE(i) + 0x0050)
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#define TIMERS_WDT_STG0_HOLD 0xFFFFFFFF
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#define TIMERS_WDT_STG0_HOLD_S 0
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#define WDTCONFIG3(i) (DR_REG_TIMERS_BASE(i) + 0x0054)
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#define TIMERS_WDT_STG1_HOLD 0xFFFFFFFF
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#define TIMERS_WDT_STG1_HOLD_S 0
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#define WDTCONFIG4(i) (DR_REG_TIMERS_BASE(i) + 0x0058)
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#define TIMERS_WDT_STG2_HOLD 0xFFFFFFFF
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#define TIMERS_WDT_STG2_HOLD_S 0
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#define WDTCONFIG5(i) (DR_REG_TIMERS_BASE(i) + 0x005c)
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#define TIMERS_WDT_STG3_HOLD 0xFFFFFFFF
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#define TIMERS_WDT_STG3_HOLD_S 0
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#define WDTFEED(i) (DR_REG_TIMERS_BASE(i) + 0x0060)
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#define TIMERS_WDT_FEED 0xFFFFFFFF
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#define TIMERS_WDT_FEED_S 0
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#define WDTWPROTECT(i) (DR_REG_TIMERS_BASE(i) + 0x0064)
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#define TIMERS_WDT_WKEY 0xFFFFFFFF
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#define TIMERS_WDT_WKEY_S 0
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#define RTCCALICFG(i) (DR_REG_TIMERS_BASE(i) + 0x0068)
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#define TIMERS_RTC_CALI_START (BIT(31))
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#define TIMERS_RTC_CALI_START_S 31
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#define TIMERS_RTC_CALI_MAX 0x00007FFF
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#define TIMERS_RTC_CALI_MAX_S 16
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#define TIMERS_RTC_CALI_RDY (BIT(15))
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#define TIMERS_RTC_CALI_RDY_S 15
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#define TIMERS_RTC_CALI_CLK_SEL 0x00000003
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#define TIMERS_RTC_CALI_CLK_SEL_S 13
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#define TIMERS_RTC_CALI_START_CYCLING (BIT(12))
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#define TIMERS_RTC_CALI_START_CYCLING_S 12
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#define RTCCALICFG1(i) (DR_REG_TIMERS_BASE(i) + 0x006c)
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#define TIMERS_RTC_CALI_VALUE 0x01FFFFFF
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#define TIMERS_RTC_CALI_VALUE_S 7
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#define LACTCONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0070)
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#define TIMERS_LACT_EN (BIT(31))
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#define TIMERS_LACT_EN_S 31
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#define TIMERS_LACT_INCREASE (BIT(30))
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#define TIMERS_LACT_INCREASE_S 30
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#define TIMERS_LACT_AUTORELOAD (BIT(29))
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#define TIMERS_LACT_AUTORELOAD_S 29
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#define TIMERS_LACT_DIVIDER 0x0000FFFF
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#define TIMERS_LACT_DIVIDER_S 13
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#define TIMERS_LACT_EDGE_INT_EN (BIT(12))
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#define TIMERS_LACT_EDGE_INT_EN_S 12
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#define TIMERS_LACT_LEVEL_INT_EN (BIT(11))
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#define TIMERS_LACT_LEVEL_INT_EN_S 11
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#define TIMERS_LACT_ALARM_EN (BIT(10))
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#define TIMERS_LACT_ALARM_EN_S 10
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#define TIMERS_LACT_LAC_EN (BIT(9))
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#define TIMERS_LACT_LAC_EN_S 9
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#define TIMERS_LACT_CPST_EN (BIT(8))
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#define TIMERS_LACT_CPST_EN_S 8
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#define TIMERS_LACT_RTC_ONLY (BIT(7))
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#define TIMERS_LACT_RTC_ONLY_S 7
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#define LACTRTC(i) (DR_REG_TIMERS_BASE(i) + 0x0074)
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#define TIMERS_LACT_RTC_STEP_LEN 0x03FFFFFF
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#define TIMERS_LACT_RTC_STEP_LEN_S 6
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#define LACTLO(i) (DR_REG_TIMERS_BASE(i) + 0x0078)
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#define TIMERS_LACT_LO 0xFFFFFFFF
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#define TIMERS_LACT_LO_S 0
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#define LACTHI(i) (DR_REG_TIMERS_BASE(i) + 0x007c)
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#define TIMERS_LACT_HI 0xFFFFFFFF
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#define TIMERS_LACT_HI_S 0
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#define LACTUPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0080)
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#define TIMERS_LACT_UPDATE 0xFFFFFFFF
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#define TIMERS_LACT_UPDATE_S 0
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#define LACTALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0084)
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#define TIMERS_LACT_ALARM_LO 0xFFFFFFFF
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#define TIMERS_LACT_ALARM_LO_S 0
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#define LACTALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0088)
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#define TIMERS_LACT_ALARM_HI 0xFFFFFFFF
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#define TIMERS_LACT_ALARM_HI_S 0
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#define LACTLOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x008c)
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#define TIMERS_LACT_LOAD_LO 0xFFFFFFFF
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#define TIMERS_LACT_LOAD_LO_S 0
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#define LACTLOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0090)
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#define TIMERS_LACT_LOAD_HI 0xFFFFFFFF
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#define TIMERS_LACT_LOAD_HI_S 0
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#define LACTLOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0094)
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#define TIMERS_LACT_LOAD 0xFFFFFFFF
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#define TIMERS_LACT_LOAD_S 0
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#define INT_ENA_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x0098)
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#define TIMERS_LACT_INT_ENA (BIT(3))
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#define TIMERS_LACT_INT_ENA_S 3
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#define TIMERS_WDT_INT_ENA (BIT(2))
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#define TIMERS_WDT_INT_ENA_S 2
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#define TIMERS_T1_INT_ENA (BIT(1))
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#define TIMERS_T1_INT_ENA_S 1
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#define TIMERS_T0_INT_ENA (BIT(0))
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#define TIMERS_T0_INT_ENA_S 0
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#define INT_RAW_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x009c)
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#define TIMERS_LACT_INT_RAW (BIT(3))
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#define TIMERS_LACT_INT_RAW_S 3
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#define TIMERS_WDT_INT_RAW (BIT(2))
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#define TIMERS_WDT_INT_RAW_S 2
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#define TIMERS_T1_INT_RAW (BIT(1))
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#define TIMERS_T1_INT_RAW_S 1
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#define TIMERS_T0_INT_RAW (BIT(0))
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#define TIMERS_T0_INT_RAW_S 0
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#define INT_ST_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a0)
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#define TIMERS_LACT_INT_ST (BIT(3))
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#define TIMERS_LACT_INT_ST_S 3
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#define TIMERS_WDT_INT_ST (BIT(2))
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#define TIMERS_WDT_INT_ST_S 2
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#define TIMERS_T1_INT_ST (BIT(1))
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#define TIMERS_T1_INT_ST_S 1
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#define TIMERS_T0_INT_ST (BIT(0))
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#define TIMERS_T0_INT_ST_S 0
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#define INT_CLR_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a4)
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#define TIMERS_LACT_INT_CLR (BIT(3))
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#define TIMERS_LACT_INT_CLR_S 3
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#define TIMERS_WDT_INT_CLR (BIT(2))
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#define TIMERS_WDT_INT_CLR_S 2
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#define TIMERS_T1_INT_CLR (BIT(1))
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#define TIMERS_T1_INT_CLR_S 1
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#define TIMERS_T0_INT_CLR (BIT(0))
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#define TIMERS_T0_INT_CLR_S 0
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#define NTIMERS_DATE(i) (DR_REG_TIMERS_BASE(i) + 0x00f8)
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#define TIMERS_NTIMERS_DATE 0x0FFFFFFF
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#define TIMERS_NTIMERS_DATE_S 0
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#define TIMERS_NTIMERS_DATE_VERSION 0x1604290
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#define REGCLK(i) (DR_REG_TIMERS_BASE(i) + 0x00fc)
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#define TIMERS_CLK_EN (BIT(31))
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#define TIMERS_CLK_EN_S 31
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#endif /* _SOC_TIMER_REG_H_ */
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