176 lines
6.9 KiB
C
176 lines
6.9 KiB
C
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#include <stdlib.h>
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#include "rom/ets_sys.h"
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#include "rom/rtc.h"
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#include "rom/uart.h"
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#include "rom/gpio.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc_io_reg.h"
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#include "soc/sens_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/apb_ctrl_reg.h"
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#include "i2c_rtc_clk.h"
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#include "soc_log.h"
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#include "sdkconfig.h"
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#include "xtensa/core-macros.h"
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#include "rtc_clk_common.h"
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/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
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* 10 cycles will take approximately 300 microseconds.
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*/
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#define XTAL_FREQ_EST_CYCLES 10
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static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate();
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static const char* TAG = "rtc_clk_init";
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void rtc_clk_init(rtc_clk_config_t cfg)
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{
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rtc_cpu_freq_config_t old_config, new_config;
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/* If we get a TG WDT system reset while running at 240MHz,
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* DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz
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* APB and CPU frequencies after reset. This will cause issues with XTAL
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* frequency estimation, so we switch to XTAL frequency first.
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*
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* Ideally we would only do this if RTC_CNTL_SOC_CLK_SEL == PLL and
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* PLL is configured for 480M, but it takes less time to switch to 40M and
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* run the following code than querying the PLL does.
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*/
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if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) == RTC_CNTL_SOC_CLK_SEL_PLL) {
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/* We don't know actual XTAL frequency yet, assume 40MHz.
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* REF_TICK divider will be corrected below, once XTAL frequency is
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* determined.
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*/
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rtc_clk_cpu_freq_to_xtal(40, 1);
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}
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/* Set tuning parameters for 8M and 150k clocks.
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* Note: this doesn't attempt to set the clocks to precise frequencies.
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* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
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* - SCK_DCAP value controls tuning of 150k clock.
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* The higher the value of DCAP is, the lower is the frequency.
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* - CK8M_DFREQ value controls tuning of 8M clock.
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* CLK_8M_DFREQ constant gives the best temperature characteristics.
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*/
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
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/* Configure 8M clock division */
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div);
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/* Enable the internal bus used to configure PLLs */
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SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
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CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
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/* Estimate XTAL frequency */
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rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
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if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
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if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
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/* XTAL frequency has already been set, use existing value */
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xtal_freq = rtc_clk_xtal_freq_get();
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} else {
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/* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
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xtal_freq = rtc_clk_xtal_freq_estimate();
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if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
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SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
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xtal_freq = RTC_XTAL_FREQ_26M;
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}
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}
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} else if (!clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
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/* Exact frequency was set in sdkconfig, but still warn if autodetected
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* frequency is different. If autodetection failed, worst case we get a
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* bit of garbage output.
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*/
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rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
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if (est_xtal_freq != xtal_freq) {
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SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
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xtal_freq, est_xtal_freq);
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}
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}
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uart_tx_wait_idle(0);
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rtc_clk_xtal_freq_update(xtal_freq);
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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/* Set CPU frequency */
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rtc_clk_cpu_freq_get_config(&old_config);
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uint32_t freq_before = old_config.freq_mhz;
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bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
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assert(res && "invalid CPU frequency value");
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/* Configure REF_TICK */
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REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, xtal_freq - 1);
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REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, APB_CLK_FREQ / MHZ - 1); /* Under PLL, APB frequency is always 80MHz */
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/* Re-calculate the ccount to make time calculation correct. */
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XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * cfg.cpu_freq_mhz / freq_before );
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/* Slow & fast clocks setup */
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if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
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rtc_clk_32k_enable(true);
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}
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if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
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bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
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rtc_clk_8m_enable(true, need_8md256);
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}
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rtc_clk_fast_freq_set(cfg.fast_freq);
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rtc_clk_slow_freq_set(cfg.slow_freq);
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}
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static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
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{
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/* Enable 8M/256 clock if needed */
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const bool clk_8m_enabled = rtc_clk_8m_enabled();
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const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
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if (!clk_8md256_enabled) {
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rtc_clk_8m_enable(true, true);
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}
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uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
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/* cal_val contains period of 8M/256 clock in XTAL clock cycles
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* (shifted by RTC_CLK_CAL_FRACT bits).
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* Xtal frequency will be (cal_val * 8M / 256) / 2^19
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*/
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uint32_t freq_mhz = (cal_val * RTC_FAST_CLK_FREQ_APPROX / MHZ / 256 ) >> RTC_CLK_CAL_FRACT;
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/* Guess the XTAL type. For now, only 40 and 26MHz are supported.
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*/
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switch (freq_mhz) {
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case 21 ... 31:
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return RTC_XTAL_FREQ_26M;
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case 32 ... 33:
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SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
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return RTC_XTAL_FREQ_26M;
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case 34 ... 35:
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SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
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return RTC_XTAL_FREQ_40M;
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case 36 ... 45:
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return RTC_XTAL_FREQ_40M;
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default:
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SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
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return RTC_XTAL_FREQ_AUTO;
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}
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/* Restore 8M and 8md256 clocks to original state */
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rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
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}
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