491 lines
17 KiB
C
491 lines
17 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_pm.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/queue.h"
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#include "freertos/semphr.h"
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#include "freertos/task.h"
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#include "soc/sdmmc_periph.h"
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#include "soc/soc_memory_layout.h"
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#include "driver/sdmmc_types.h"
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#include "driver/sdmmc_defs.h"
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#include "driver/sdmmc_host.h"
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#include "sdmmc_private.h"
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/* Number of DMA descriptors used for transfer.
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* Increasing this value above 4 doesn't improve performance for the usual case
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* of SD memory cards (most data transfers are multiples of 512 bytes).
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*/
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#define SDMMC_DMA_DESC_CNT 4
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static const char* TAG = "sdmmc_req";
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typedef enum {
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SDMMC_IDLE,
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SDMMC_SENDING_CMD,
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SDMMC_SENDING_DATA,
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SDMMC_BUSY,
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} sdmmc_req_state_t;
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typedef struct {
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uint8_t* ptr;
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size_t size_remaining;
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size_t next_desc;
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size_t desc_remaining;
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} sdmmc_transfer_state_t;
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const uint32_t SDMMC_DATA_ERR_MASK =
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SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC |
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SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE |
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SDMMC_INTMASK_EBE;
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const uint32_t SDMMC_DMA_DONE_MASK =
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SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI |
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SDMMC_IDMAC_INTMASK_NI;
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const uint32_t SDMMC_CMD_ERR_MASK =
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SDMMC_INTMASK_RTO |
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SDMMC_INTMASK_RCRC |
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SDMMC_INTMASK_RESP_ERR;
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static sdmmc_desc_t s_dma_desc[SDMMC_DMA_DESC_CNT];
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static sdmmc_transfer_state_t s_cur_transfer = { 0 };
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static QueueHandle_t s_request_mutex;
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static bool s_is_app_cmd; // This flag is set if the next command is an APP command
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#ifdef CONFIG_PM_ENABLE
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static esp_pm_lock_handle_t s_pm_lock;
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#endif
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static esp_err_t handle_idle_state_events();
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static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd);
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static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state,
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sdmmc_event_t* unhandled_events);
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static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd,
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sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events);
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static void process_command_response(uint32_t status, sdmmc_command_t* cmd);
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static void fill_dma_descriptors(size_t num_desc);
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static size_t get_free_descriptors_count();
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static bool wait_for_busy_cleared(int timeout_ms);
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esp_err_t sdmmc_host_transaction_handler_init()
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{
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assert(s_request_mutex == NULL);
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s_request_mutex = xSemaphoreCreateMutex();
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if (!s_request_mutex) {
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return ESP_ERR_NO_MEM;
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}
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s_is_app_cmd = false;
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#ifdef CONFIG_PM_ENABLE
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esp_err_t err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "sdmmc", &s_pm_lock);
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if (err != ESP_OK) {
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vSemaphoreDelete(s_request_mutex);
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s_request_mutex = NULL;
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return err;
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}
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#endif
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return ESP_OK;
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}
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void sdmmc_host_transaction_handler_deinit()
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{
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assert(s_request_mutex);
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_delete(s_pm_lock);
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s_pm_lock = NULL;
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#endif
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vSemaphoreDelete(s_request_mutex);
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s_request_mutex = NULL;
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}
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esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo)
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{
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esp_err_t ret;
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xSemaphoreTake(s_request_mutex, portMAX_DELAY);
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_acquire(s_pm_lock);
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#endif
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// dispose of any events which happened asynchronously
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handle_idle_state_events();
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// convert cmdinfo to hardware register value
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sdmmc_hw_cmd_t hw_cmd = make_hw_cmd(cmdinfo);
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if (cmdinfo->data) {
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// Length should be either <4 or >=4 and =0 (mod 4).
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if (cmdinfo->datalen >= 4 && cmdinfo->datalen % 4 != 0) {
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ESP_LOGD(TAG, "%s: invalid size: total=%d",
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__func__, cmdinfo->datalen);
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ret = ESP_ERR_INVALID_SIZE;
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goto out;
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}
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if ((intptr_t) cmdinfo->data % 4 != 0 ||
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!esp_ptr_dma_capable(cmdinfo->data)) {
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ESP_LOGD(TAG, "%s: buffer %p can not be used for DMA", __func__, cmdinfo->data);
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ret = ESP_ERR_INVALID_ARG;
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goto out;
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}
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// this clears "owned by IDMAC" bits
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memset(s_dma_desc, 0, sizeof(s_dma_desc));
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// initialize first descriptor
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s_dma_desc[0].first_descriptor = 1;
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// save transfer info
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s_cur_transfer.ptr = (uint8_t*) cmdinfo->data;
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s_cur_transfer.size_remaining = cmdinfo->datalen;
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s_cur_transfer.next_desc = 0;
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s_cur_transfer.desc_remaining = (cmdinfo->datalen + SDMMC_DMA_MAX_BUF_LEN - 1) / SDMMC_DMA_MAX_BUF_LEN;
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// prepare descriptors
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fill_dma_descriptors(SDMMC_DMA_DESC_CNT);
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// write transfer info into hardware
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sdmmc_host_dma_prepare(&s_dma_desc[0], cmdinfo->blklen, cmdinfo->datalen);
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}
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// write command into hardware, this also sends the command to the card
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ret = sdmmc_host_start_command(slot, hw_cmd, cmdinfo->arg);
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if (ret != ESP_OK) {
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goto out;
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}
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// process events until transfer is complete
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cmdinfo->error = ESP_OK;
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sdmmc_req_state_t state = SDMMC_SENDING_CMD;
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sdmmc_event_t unhandled_events = { 0 };
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while (state != SDMMC_IDLE) {
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ret = handle_event(cmdinfo, &state, &unhandled_events);
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if (ret != ESP_OK) {
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break;
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}
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}
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if (ret == ESP_OK && (cmdinfo->flags & SCF_WAIT_BUSY)) {
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if (!wait_for_busy_cleared(cmdinfo->timeout_ms)) {
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ret = ESP_ERR_TIMEOUT;
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}
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}
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s_is_app_cmd = (ret == ESP_OK && cmdinfo->opcode == MMC_APP_CMD);
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out:
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_release(s_pm_lock);
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#endif
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xSemaphoreGive(s_request_mutex);
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return ret;
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}
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static size_t get_free_descriptors_count()
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{
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const size_t next = s_cur_transfer.next_desc;
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size_t count = 0;
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/* Starting with the current DMA descriptor, count the number of
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* descriptors which have 'owned_by_idmac' set to 0. These are the
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* descriptors already processed by the DMA engine.
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*/
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for (size_t i = 0; i < SDMMC_DMA_DESC_CNT; ++i) {
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sdmmc_desc_t* desc = &s_dma_desc[(next + i) % SDMMC_DMA_DESC_CNT];
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if (desc->owned_by_idmac) {
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break;
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}
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++count;
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if (desc->next_desc_ptr == NULL) {
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/* final descriptor in the chain */
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break;
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}
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}
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return count;
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}
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static void fill_dma_descriptors(size_t num_desc)
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{
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for (size_t i = 0; i < num_desc; ++i) {
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if (s_cur_transfer.size_remaining == 0) {
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return;
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}
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const size_t next = s_cur_transfer.next_desc;
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sdmmc_desc_t* desc = &s_dma_desc[next];
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assert(!desc->owned_by_idmac);
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size_t size_to_fill =
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(s_cur_transfer.size_remaining < SDMMC_DMA_MAX_BUF_LEN) ?
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s_cur_transfer.size_remaining : SDMMC_DMA_MAX_BUF_LEN;
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bool last = size_to_fill == s_cur_transfer.size_remaining;
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desc->last_descriptor = last;
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desc->second_address_chained = 1;
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desc->owned_by_idmac = 1;
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desc->buffer1_ptr = s_cur_transfer.ptr;
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desc->next_desc_ptr = (last) ? NULL : &s_dma_desc[(next + 1) % SDMMC_DMA_DESC_CNT];
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assert(size_to_fill < 4 || size_to_fill % 4 == 0);
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desc->buffer1_size = (size_to_fill + 3) & (~3);
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s_cur_transfer.size_remaining -= size_to_fill;
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s_cur_transfer.ptr += size_to_fill;
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s_cur_transfer.next_desc = (s_cur_transfer.next_desc + 1) % SDMMC_DMA_DESC_CNT;
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ESP_LOGV(TAG, "fill %d desc=%d rem=%d next=%d last=%d sz=%d",
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num_desc, next, s_cur_transfer.size_remaining,
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s_cur_transfer.next_desc, desc->last_descriptor, desc->buffer1_size);
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}
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}
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static esp_err_t handle_idle_state_events()
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{
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/* Handle any events which have happened in between transfers.
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* Under current assumptions (no SDIO support) only card detect events
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* can happen in the idle state.
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*/
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sdmmc_event_t evt;
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while (sdmmc_host_wait_for_event(0, &evt) == ESP_OK) {
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if (evt.sdmmc_status & SDMMC_INTMASK_CD) {
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ESP_LOGV(TAG, "card detect event");
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evt.sdmmc_status &= ~SDMMC_INTMASK_CD;
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}
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if (evt.sdmmc_status != 0 || evt.dma_status != 0) {
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ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08x %08x",
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evt.sdmmc_status, evt.dma_status);
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}
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}
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return ESP_OK;
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}
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static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state,
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sdmmc_event_t* unhandled_events)
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{
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sdmmc_event_t event;
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esp_err_t err = sdmmc_host_wait_for_event(cmd->timeout_ms / portTICK_PERIOD_MS, &event);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "sdmmc_host_wait_for_event returned 0x%x", err);
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if (err == ESP_ERR_TIMEOUT) {
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sdmmc_host_dma_stop();
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}
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return err;
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}
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ESP_LOGV(TAG, "sdmmc_handle_event: event %08x %08x, unhandled %08x %08x",
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event.sdmmc_status, event.dma_status,
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unhandled_events->sdmmc_status, unhandled_events->dma_status);
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event.sdmmc_status |= unhandled_events->sdmmc_status;
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event.dma_status |= unhandled_events->dma_status;
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process_events(event, cmd, state, unhandled_events);
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ESP_LOGV(TAG, "sdmmc_handle_event: events unhandled: %08x %08x", unhandled_events->sdmmc_status, unhandled_events->dma_status);
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return ESP_OK;
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}
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static bool cmd_needs_auto_stop(const sdmmc_command_t* cmd)
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{
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/* SDMMC host needs an "auto stop" flag for the following commands: */
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return cmd->datalen > 0 &&
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(cmd->opcode == MMC_WRITE_BLOCK_MULTIPLE ||
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cmd->opcode == MMC_READ_BLOCK_MULTIPLE ||
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cmd->opcode == MMC_WRITE_DAT_UNTIL_STOP ||
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cmd->opcode == MMC_READ_DAT_UNTIL_STOP);
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}
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static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd)
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{
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sdmmc_hw_cmd_t res = { 0 };
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res.cmd_index = cmd->opcode;
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if (cmd->opcode == MMC_STOP_TRANSMISSION) {
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res.stop_abort_cmd = 1;
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} else if (cmd->opcode == MMC_GO_IDLE_STATE) {
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res.send_init = 1;
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} else {
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res.wait_complete = 1;
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}
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if (cmd->opcode == MMC_GO_IDLE_STATE) {
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res.send_init = 1;
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}
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if (cmd->flags & SCF_RSP_PRESENT) {
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res.response_expect = 1;
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if (cmd->flags & SCF_RSP_136) {
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res.response_long = 1;
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}
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}
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if (cmd->flags & SCF_RSP_CRC) {
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res.check_response_crc = 1;
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}
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res.use_hold_reg = 1;
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if (cmd->data) {
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res.data_expected = 1;
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if ((cmd->flags & SCF_CMD_READ) == 0) {
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res.rw = 1;
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}
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assert(cmd->datalen % cmd->blklen == 0);
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res.send_auto_stop = cmd_needs_auto_stop(cmd) ? 1 : 0;
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}
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ESP_LOGV(TAG, "%s: opcode=%d, rexp=%d, crc=%d, auto_stop=%d", __func__,
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res.cmd_index, res.response_expect, res.check_response_crc,
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res.send_auto_stop);
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return res;
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}
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static void process_command_response(uint32_t status, sdmmc_command_t* cmd)
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{
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if (cmd->flags & SCF_RSP_PRESENT) {
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if (cmd->flags & SCF_RSP_136) {
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/* Destination is 4-byte aligned, can memcopy from peripheral registers */
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memcpy(cmd->response, (uint32_t*) SDMMC.resp, 4 * sizeof(uint32_t));
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} else {
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cmd->response[0] = SDMMC.resp[0];
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cmd->response[1] = 0;
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cmd->response[2] = 0;
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cmd->response[3] = 0;
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}
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}
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esp_err_t err = ESP_OK;
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if (status & SDMMC_INTMASK_RTO) {
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// response timeout is only possible when response is expected
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assert(cmd->flags & SCF_RSP_PRESENT);
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err = ESP_ERR_TIMEOUT;
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} else if ((cmd->flags & SCF_RSP_CRC) && (status & SDMMC_INTMASK_RCRC)) {
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err = ESP_ERR_INVALID_CRC;
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} else if (status & SDMMC_INTMASK_RESP_ERR) {
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err = ESP_ERR_INVALID_RESPONSE;
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}
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if (err != ESP_OK) {
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cmd->error = err;
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if (cmd->data) {
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sdmmc_host_dma_stop();
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}
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ESP_LOGD(TAG, "%s: error 0x%x (status=%08x)", __func__, err, status);
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}
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}
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static void process_data_status(uint32_t status, sdmmc_command_t* cmd)
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{
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if (status & SDMMC_DATA_ERR_MASK) {
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if (status & SDMMC_INTMASK_DTO) {
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cmd->error = ESP_ERR_TIMEOUT;
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} else if (status & SDMMC_INTMASK_DCRC) {
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cmd->error = ESP_ERR_INVALID_CRC;
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} else if ((status & SDMMC_INTMASK_EBE) &&
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(cmd->flags & SCF_CMD_READ) == 0) {
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cmd->error = ESP_ERR_TIMEOUT;
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} else {
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cmd->error = ESP_FAIL;
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}
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SDMMC.ctrl.fifo_reset = 1;
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}
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if (cmd->error != 0) {
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if (cmd->data) {
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sdmmc_host_dma_stop();
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}
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ESP_LOGD(TAG, "%s: error 0x%x (status=%08x)", __func__, cmd->error, status);
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}
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}
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static inline bool mask_check_and_clear(uint32_t* state, uint32_t mask) {
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bool ret = ((*state) & mask) != 0;
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*state &= ~mask;
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return ret;
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}
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static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd,
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sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events)
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{
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const char* const s_state_names[] __attribute__((unused)) = {
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"IDLE",
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"SENDING_CMD",
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"SENDIND_DATA",
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"BUSY"
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};
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sdmmc_event_t orig_evt = evt;
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ESP_LOGV(TAG, "%s: state=%s evt=%x dma=%x", __func__, s_state_names[*pstate],
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evt.sdmmc_status, evt.dma_status);
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sdmmc_req_state_t next_state = *pstate;
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sdmmc_req_state_t state = (sdmmc_req_state_t) -1;
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while (next_state != state) {
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state = next_state;
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switch (state) {
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case SDMMC_IDLE:
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break;
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case SDMMC_SENDING_CMD:
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if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) {
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process_command_response(orig_evt.sdmmc_status, cmd);
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break; // Need to wait for the CMD_DONE interrupt
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}
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if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_CMD_DONE)) {
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process_command_response(orig_evt.sdmmc_status, cmd);
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if (cmd->error != ESP_OK) {
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next_state = SDMMC_IDLE;
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break;
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}
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if (cmd->data == NULL) {
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next_state = SDMMC_IDLE;
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} else {
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next_state = SDMMC_SENDING_DATA;
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}
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}
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break;
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case SDMMC_SENDING_DATA:
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if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_DATA_ERR_MASK)) {
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process_data_status(orig_evt.sdmmc_status, cmd);
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sdmmc_host_dma_stop();
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}
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if (mask_check_and_clear(&evt.dma_status, SDMMC_DMA_DONE_MASK)) {
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s_cur_transfer.desc_remaining--;
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if (s_cur_transfer.size_remaining) {
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int desc_to_fill = get_free_descriptors_count();
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fill_dma_descriptors(desc_to_fill);
|
|
sdmmc_host_dma_resume();
|
|
}
|
|
if (s_cur_transfer.desc_remaining == 0) {
|
|
next_state = SDMMC_BUSY;
|
|
}
|
|
}
|
|
if (orig_evt.sdmmc_status & (SDMMC_INTMASK_SBE | SDMMC_INTMASK_DATA_OVER)) {
|
|
// On start bit error, DATA_DONE interrupt will not be generated
|
|
next_state = SDMMC_IDLE;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case SDMMC_BUSY:
|
|
if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_DATA_OVER)) {
|
|
break;
|
|
}
|
|
process_data_status(orig_evt.sdmmc_status, cmd);
|
|
next_state = SDMMC_IDLE;
|
|
break;
|
|
}
|
|
ESP_LOGV(TAG, "%s state=%s next_state=%s", __func__, s_state_names[state], s_state_names[next_state]);
|
|
}
|
|
*pstate = state;
|
|
*unhandled_events = evt;
|
|
return ESP_OK;
|
|
}
|
|
|
|
static bool wait_for_busy_cleared(int timeout_ms)
|
|
{
|
|
if (timeout_ms == 0) {
|
|
return !sdmmc_host_card_busy();
|
|
}
|
|
|
|
/* It would have been nice to do this without polling, however the peripheral
|
|
* can only generate Busy Clear Interrupt for data write commands, and waiting
|
|
* for busy clear is mostly needed for other commands such as MMC_SWITCH.
|
|
*/
|
|
int timeout_ticks = (timeout_ms + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS;
|
|
while (timeout_ticks-- > 0) {
|
|
if (!sdmmc_host_card_busy()) {
|
|
return true;
|
|
}
|
|
vTaskDelay(1);
|
|
}
|
|
return false;
|
|
}
|
|
|