// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. #ifndef _SOC_DPORT_REG_H_ #define _SOC_DPORT_REG_H_ #include "soc.h" #define PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) #define DPORT_PRO_BOOT_REMAP (BIT(0)) #define DPORT_PRO_BOOT_REMAP_S 0 #define APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) #define DPORT_APP_BOOT_REMAP (BIT(0)) #define DPORT_APP_BOOT_REMAP_S 0 #define DPORT_ACCESS_CHECK (DR_REG_DPORT_BASE + 0x008) #define DPORT_DPORT_ACCESS_CHECK_APP (BIT(8)) #define DPORT_DPORT_ACCESS_CHECK_APP_S 8 #define DPORT_DPORT_ACCESS_CHECK_PRO (BIT(0)) #define DPORT_DPORT_ACCESS_CHECK_PRO_S 0 #define PRO_DPORT_APB_MASK0 (DR_REG_DPORT_BASE + 0x00C) #define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF #define DPORT_PRODPORT_APB_MASK0_S 0 #define PRO_DPORT_APB_MASK1 (DR_REG_DPORT_BASE + 0x010) #define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF #define DPORT_PRODPORT_APB_MASK1_S 0 #define APP_DPORT_APB_MASK0 (DR_REG_DPORT_BASE + 0x014) #define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF #define DPORT_APPDPORT_APB_MASK0_S 0 #define APP_DPORT_APB_MASK1 (DR_REG_DPORT_BASE + 0x018) #define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF #define DPORT_APPDPORT_APB_MASK1_S 0 #define PERI_CLK_EN (DR_REG_DPORT_BASE + 0x01C) #define DPORT_PERI_CLK_EN 0xFFFFFFFF #define DPORT_PERI_CLK_EN_S 0 #define PERI_RST_EN (DR_REG_DPORT_BASE + 0x020) #define DPORT_PERI_RST_EN 0xFFFFFFFF #define DPORT_PERI_RST_EN_S 0 #define WIFI_BB_CFG (DR_REG_DPORT_BASE + 0x024) #define DPORT_WIFI_BB_CFG 0xFFFFFFFF #define DPORT_WIFI_BB_CFG_S 0 #define WIFI_BB_CFG_2 (DR_REG_DPORT_BASE + 0x028) #define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF #define DPORT_WIFI_BB_CFG_2_S 0 #define APPCPU_CTRL_REG_A (DR_REG_DPORT_BASE + 0x02C) #define DPORT_APPCPU_RESETTING (BIT(0)) #define DPORT_APPCPU_RESETTING_S 0 #define APPCPU_CTRL_REG_B (DR_REG_DPORT_BASE + 0x030) #define DPORT_APPCPU_CLKGATE_EN (BIT(0)) #define DPORT_APPCPU_CLKGATE_EN_S 0 #define APPCPU_CTRL_REG_C (DR_REG_DPORT_BASE + 0x034) #define DPORT_APPCPU_RUNSTALL (BIT(0)) #define DPORT_APPCPU_RUNSTALL_S 0 #define APPCPU_CTRL_REG_D (DR_REG_DPORT_BASE + 0x038) #define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF #define DPORT_APPCPU_BOOT_ADDR_S 0 #define CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) #define DPORT_FAST_CLK_RTC_SEL (BIT(3)) #define DPORT_FAST_CLK_RTC_SEL_S 3 #define DPORT_LOWSPEED_CLK_SEL (BIT(2)) #define DPORT_LOWSPEED_CLK_SEL_S 2 #define DPORT_CPUPERIOD_SEL 0x00000003 #define DPORT_CPUPERIOD_SEL_S 0 #define PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) #define DPORT_PRO_DRAM_HL (BIT(16)) #define DPORT_PRO_DRAM_HL_S 16 #define DPORT_SLAVE_REQ (BIT(15)) #define DPORT_SLAVE_REQ_S 15 #define DPORT_AHB_SPI_REQ (BIT(14)) #define DPORT_AHB_SPI_REQ_S 14 #define DPORT_PRO_SLAVE_REQ (BIT(13)) #define DPORT_PRO_SLAVE_REQ_S 13 #define DPORT_PRO_AHB_SPI_REQ (BIT(12)) #define DPORT_PRO_AHB_SPI_REQ_S 12 #define DPORT_PRO_DRAM_SPLIT (BIT(11)) #define DPORT_PRO_DRAM_SPLIT_S 11 #define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) #define DPORT_PRO_SINGLE_IRAM_ENA_S 10 #define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) #define DPORT_PRO_CACHE_LOCK_3_EN_S 9 #define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) #define DPORT_PRO_CACHE_LOCK_2_EN_S 8 #define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) #define DPORT_PRO_CACHE_LOCK_1_EN_S 7 #define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) #define DPORT_PRO_CACHE_LOCK_0_EN_S 6 #define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) #define DPORT_PRO_CACHE_FLUSH_DONE_S 5 #define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) #define DPORT_PRO_CACHE_FLUSH_ENA_S 4 #define DPORT_PRO_CACHE_ENABLE (BIT(3)) #define DPORT_PRO_CACHE_ENABLE_S 3 #define DPORT_PRO_CACHE_MODE (BIT(2)) #define DPORT_PRO_CACHE_MODE_S 2 #define PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) #define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) #define DPORT_PRO_CACHE_MMU_IA_CLR_S 13 #define DPORT_PRO_CMMU_PD (BIT(12)) #define DPORT_PRO_CMMU_PD_S 12 #define DPORT_PRO_CMMU_FORCE_ON (BIT(11)) #define DPORT_PRO_CMMU_FORCE_ON_S 11 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 #define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) #define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 #define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) #define DPORT_PRO_CACHE_MASK_DROM0_S 4 #define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) #define DPORT_PRO_CACHE_MASK_DRAM1_S 3 #define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) #define DPORT_PRO_CACHE_MASK_IROM0_S 2 #define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) #define DPORT_PRO_CACHE_MASK_IRAM1_S 1 #define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) #define DPORT_PRO_CACHE_MASK_IRAM0_S 0 #define PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 #define PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 #define PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 #define PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 #define APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) #define DPORT_APP_DRAM_HL (BIT(14)) #define DPORT_APP_DRAM_HL_S 14 #define DPORT_APP_SLAVE_REQ (BIT(13)) #define DPORT_APP_SLAVE_REQ_S 13 #define DPORT_APP_AHB_SPI_REQ (BIT(12)) #define DPORT_APP_AHB_SPI_REQ_S 12 #define DPORT_APP_DRAM_SPLIT (BIT(11)) #define DPORT_APP_DRAM_SPLIT_S 11 #define DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) #define DPORT_APP_SINGLE_IRAM_ENA_S 10 #define DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) #define DPORT_APP_CACHE_LOCK_3_EN_S 9 #define DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) #define DPORT_APP_CACHE_LOCK_2_EN_S 8 #define DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) #define DPORT_APP_CACHE_LOCK_1_EN_S 7 #define DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) #define DPORT_APP_CACHE_LOCK_0_EN_S 6 #define DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) #define DPORT_APP_CACHE_FLUSH_DONE_S 5 #define DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) #define DPORT_APP_CACHE_FLUSH_ENA_S 4 #define DPORT_APP_CACHE_ENABLE (BIT(3)) #define DPORT_APP_CACHE_ENABLE_S 3 #define DPORT_APP_CACHE_MODE (BIT(2)) #define DPORT_APP_CACHE_MODE_S 2 #define APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) #define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) #define DPORT_APP_CACHE_MMU_IA_CLR_S 13 #define DPORT_APP_CMMU_PD (BIT(12)) #define DPORT_APP_CMMU_PD_S 12 #define DPORT_APP_CMMU_FORCE_ON (BIT(11)) #define DPORT_APP_CMMU_FORCE_ON_S 11 #define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 #define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 #define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) #define DPORT_APP_CACHE_MASK_OPSDRAM_S 5 #define DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) #define DPORT_APP_CACHE_MASK_DROM0_S 4 #define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) #define DPORT_APP_CACHE_MASK_DRAM1_S 3 #define DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) #define DPORT_APP_CACHE_MASK_IROM0_S 2 #define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) #define DPORT_APP_CACHE_MASK_IRAM1_S 1 #define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) #define DPORT_APP_CACHE_MASK_IRAM0_S 0 #define APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 #define APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 #define APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 #define APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 #define TRACEMEM_MUX_MODE (DR_REG_DPORT_BASE + 0x070) #define DPORT_TRACEMEM_MUX_MODE 0x00000003 #define DPORT_TRACEMEM_MUX_MODE_S 0 #define PRO_TRACEMEM_ENA (DR_REG_DPORT_BASE + 0x074) #define DPORT_PRO_TRACEMEM_ENA (BIT(0)) #define DPORT_PRO_TRACEMEM_ENA_S 0 #define APP_TRACEMEM_ENA (DR_REG_DPORT_BASE + 0x078) #define DPORT_APP_TRACEMEM_ENA (BIT(0)) #define DPORT_APP_TRACEMEM_ENA_S 0 #define CACHE_MUX_MODE (DR_REG_DPORT_BASE + 0x07C) #define DPORT_CACHE_MUX_MODE 0x00000003 #define DPORT_CACHE_MUX_MODE_S 0 #define IMMU_PAGE_MODE (DR_REG_DPORT_BASE + 0x080) #define DPORT_IMMU_PAGE_MODE 0x00000003 #define DPORT_IMMU_PAGE_MODE_S 1 #define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) #define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 #define DMMU_PAGE_MODE (DR_REG_DPORT_BASE + 0x084) #define DPORT_DMMU_PAGE_MODE 0x00000003 #define DPORT_DMMU_PAGE_MODE_S 1 #define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) #define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 #define ROM_MPU_ENA (DR_REG_DPORT_BASE + 0x088) #define DPORT_APP_ROM_MPU_ENA (BIT(2)) #define DPORT_APP_ROM_MPU_ENA_S 2 #define DPORT_PRO_ROM_MPU_ENA (BIT(1)) #define DPORT_PRO_ROM_MPU_ENA_S 1 #define DPORT_SHARE_ROM_MPU_ENA (BIT(0)) #define DPORT_SHARE_ROM_MPU_ENA_S 0 #define MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) #define DPORT_LSLP_MEM_PD_MASK (BIT(0)) #define DPORT_LSLP_MEM_PD_MASK_S 0 #define ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) #define DPORT_SHARE_ROM_PD 0x0000003F #define DPORT_SHARE_ROM_PD_S 2 #define DPORT_APP_ROM_PD (BIT(1)) #define DPORT_APP_ROM_PD_S 1 #define DPORT_PRO_ROM_PD (BIT(0)) #define DPORT_PRO_ROM_PD_S 0 #define ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) #define DPORT_SHARE_ROM_FO 0x0000003F #define DPORT_SHARE_ROM_FO_S 2 #define DPORT_APP_ROM_FO (BIT(1)) #define DPORT_APP_ROM_FO_S 1 #define DPORT_PRO_ROM_FO (BIT(0)) #define DPORT_PRO_ROM_FO_S 0 #define SRAM_PD_CTRL_REG_0 (DR_REG_DPORT_BASE + 0x098) #define DPORT_SRAM_PD_0 0xFFFFFFFF #define DPORT_SRAM_PD_0_S 0 #define SRAM_PD_CTRL_REG_1 (DR_REG_DPORT_BASE + 0x09C) #define DPORT_SRAM_PD_1 (BIT(0)) #define DPORT_SRAM_PD_1_S 0 #define SRAM_FO_CTRL_REG_0 (DR_REG_DPORT_BASE + 0x0A0) #define DPORT_SRAM_FO_0 0xFFFFFFFF #define DPORT_SRAM_FO_0_S 0 #define SRAM_FO_CTRL_REG_1 (DR_REG_DPORT_BASE + 0x0A4) #define DPORT_SRAM_FO_1 (BIT(0)) #define DPORT_SRAM_FO_1_S 0 #define IRAM_DRAM_AHB_SEL (DR_REG_DPORT_BASE + 0x0A8) #define DPORT_MAC_DUMP_MODE 0x00000003 #define DPORT_MAC_DUMP_MODE_S 5 #define DPORT_MASK_AHB (BIT(4)) #define DPORT_MASK_AHB_S 4 #define DPORT_MASK_APP_DRAM (BIT(3)) #define DPORT_MASK_APP_DRAM_S 3 #define DPORT_MASK_PRO_DRAM (BIT(2)) #define DPORT_MASK_PRO_DRAM_S 2 #define DPORT_MASK_APP_IRAM (BIT(1)) #define DPORT_MASK_APP_IRAM_S 1 #define DPORT_MASK_PRO_IRAM (BIT(0)) #define DPORT_MASK_PRO_IRAM_S 0 #define TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) #define DPORT_APP_CACHE_TAG_PD (BIT(9)) #define DPORT_APP_CACHE_TAG_PD_S 9 #define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) #define DPORT_APP_CACHE_TAG_FORCE_ON_S 8 #define DPORT_PRO_CACHE_TAG_PD (BIT(1)) #define DPORT_PRO_CACHE_TAG_PD_S 1 #define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) #define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 #define AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) #define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 #define DPORT_AHB_LITE_SDHOST_PID_REG_S 11 #define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) #define DPORT_AHB_LITE_MASK_APPDPORT_S 10 #define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) #define DPORT_AHB_LITE_MASK_PRODPORT_S 9 #define DPORT_AHB_LITE_MASK_SDIO (BIT(8)) #define DPORT_AHB_LITE_MASK_SDIO_S 8 #define DPORT_AHB_LITE_MASK_APP (BIT(4)) #define DPORT_AHB_LITE_MASK_APP_S 4 #define DPORT_AHB_LITE_MASK_PRO (BIT(0)) #define DPORT_AHB_LITE_MASK_PRO_S 0 #define AHB_MPU_TABLE_0 (DR_REG_DPORT_BASE + 0x0B4) #define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF #define DPORT_AHB_ACCESS_GRANT_0_S 0 #define AHB_MPU_TABLE_1 (DR_REG_DPORT_BASE + 0x0B8) #define DPORT_AHB_ACCESS_GRANT_1 0x000001FF #define DPORT_AHB_ACCESS_GRANT_1_S 0 #define HOST_INF_SEL (DR_REG_DPORT_BASE + 0x0BC) #define DPORT_LINK_DEVICE_SEL 0x000000FF #define DPORT_LINK_DEVICE_SEL_S 8 #define DPORT_PERI_IO_SWAP 0x000000FF #define DPORT_PERI_IO_SWAP_S 0 #define PERIP_CLK_EN (DR_REG_DPORT_BASE + 0x0C0) #define DPORT_PERIP_CLK_EN 0xFFFFFFFF #define DPORT_PERIP_CLK_EN_S 0 #define PERIP_RST_EN (DR_REG_DPORT_BASE + 0x0C4) #define DPORT_PERIP_RST 0xFFFFFFFF #define DPORT_PERIP_RST_S 0 #define SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) #define DPORT_SPI_DECRYPT_ENABLE (BIT(12)) #define DPORT_SPI_DECRYPT_ENABLE_S 12 #define DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) #define DPORT_SPI_ENCRYPT_ENABLE_S 8 #define DPORT_SLAVE_SPI_MASK_APP (BIT(4)) #define DPORT_SLAVE_SPI_MASK_APP_S 4 #define DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) #define DPORT_SLAVE_SPI_MASK_PRO_S 0 #define WIFI_CLK_EN (DR_REG_DPORT_BASE + 0x0CC) #define DPORT_WIFI_CLK_EN 0xFFFFFFFF #define DPORT_WIFI_CLK_EN_S 0 #define WIFI_RST_EN (DR_REG_DPORT_BASE + 0x0D0) #define DPORT_SDIO_RST (BIT(5)) #define DPORT_MAC_RST (BIT(2)) #define DPORT_WIFI_RST 0xFFFFFFFF #define DPORT_WIFI_RST_S 0 #define BT_LPCK_DIV_INT (DR_REG_DPORT_BASE + 0x0D4) #define DPORT_BTEXTWAKEUP_REQ (BIT(12)) #define DPORT_BTEXTWAKEUP_REQ_S 12 #define DPORT_BT_LPCK_DIV_NUM 0x00000FFF #define DPORT_BT_LPCK_DIV_NUM_S 0 #define BT_LPCK_DIV_FRAC (DR_REG_DPORT_BASE + 0x0D8) #define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) #define DPORT_LPCLK_SEL_XTAL32K_S 27 #define DPORT_LPCLK_SEL_XTAL (BIT(26)) #define DPORT_LPCLK_SEL_XTAL_S 26 #define DPORT_LPCLK_SEL_8M (BIT(25)) #define DPORT_LPCLK_SEL_8M_S 25 #define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) #define DPORT_LPCLK_SEL_RTC_SLOW_S 24 #define DPORT_BT_LPCK_DIV_A 0x00000FFF #define DPORT_BT_LPCK_DIV_A_S 12 #define DPORT_BT_LPCK_DIV_B 0x00000FFF #define DPORT_BT_LPCK_DIV_B_S 0 #define CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) #define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_0_S 0 #define CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) #define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_1_S 0 #define CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) #define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_2_S 0 #define CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) #define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_3_S 0 #define PRO_INTR_STATUS_REG_0 (DR_REG_DPORT_BASE + 0x0EC) #define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_0_S 0 #define PRO_INTR_STATUS_REG_1 (DR_REG_DPORT_BASE + 0x0F0) #define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_1_S 0 #define PRO_INTR_STATUS_REG_2 (DR_REG_DPORT_BASE + 0x0F4) #define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_2_S 0 #define APP_INTR_STATUS_REG_0 (DR_REG_DPORT_BASE + 0x0F8) #define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_0_S 0 #define APP_INTR_STATUS_REG_1 (DR_REG_DPORT_BASE + 0x0FC) #define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_1_S 0 #define APP_INTR_STATUS_REG_2 (DR_REG_DPORT_BASE + 0x100) #define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_2_S 0 #define PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) #define DPORT_PRO_MAC_INTR_MAP 0x0000001F #define DPORT_PRO_MAC_INTR_MAP_S 0 #define PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) #define DPORT_PRO_MAC_NMI_MAP 0x0000001F #define DPORT_PRO_MAC_NMI_MAP_S 0 #define PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) #define DPORT_PRO_BB_INT_MAP 0x0000001F #define DPORT_PRO_BB_INT_MAP_S 0 #define PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) #define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F #define DPORT_PRO_BT_MAC_INT_MAP_S 0 #define PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) #define DPORT_PRO_BT_BB_INT_MAP 0x0000001F #define DPORT_PRO_BT_BB_INT_MAP_S 0 #define PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) #define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F #define DPORT_PRO_BT_BB_NMI_MAP_S 0 #define PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) #define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F #define DPORT_PRO_RWBT_IRQ_MAP_S 0 #define PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) #define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F #define DPORT_PRO_RWBLE_IRQ_MAP_S 0 #define PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) #define DPORT_PRO_RWBT_NMI_MAP 0x0000001F #define DPORT_PRO_RWBT_NMI_MAP_S 0 #define PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) #define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F #define DPORT_PRO_RWBLE_NMI_MAP_S 0 #define PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) #define DPORT_PRO_SLC0_INTR_MAP 0x0000001F #define DPORT_PRO_SLC0_INTR_MAP_S 0 #define PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) #define DPORT_PRO_SLC1_INTR_MAP 0x0000001F #define DPORT_PRO_SLC1_INTR_MAP_S 0 #define PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) #define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F #define DPORT_PRO_UHCI0_INTR_MAP_S 0 #define PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) #define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F #define DPORT_PRO_UHCI1_INTR_MAP_S 0 #define PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) #define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 #define PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) #define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 #define PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 #define PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 #define PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 #define PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 #define PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 #define PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 #define PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 #define PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 #define PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 #define PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 #define PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 #define PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 #define PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) #define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F #define DPORT_PRO_SPI_INTR_0_MAP_S 0 #define PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) #define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F #define DPORT_PRO_SPI_INTR_1_MAP_S 0 #define PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) #define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F #define DPORT_PRO_SPI_INTR_2_MAP_S 0 #define PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) #define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F #define DPORT_PRO_SPI_INTR_3_MAP_S 0 #define PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) #define DPORT_PRO_I2S0_INT_MAP 0x0000001F #define DPORT_PRO_I2S0_INT_MAP_S 0 #define PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) #define DPORT_PRO_I2S1_INT_MAP 0x0000001F #define DPORT_PRO_I2S1_INT_MAP_S 0 #define PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) #define DPORT_PRO_UART_INTR_MAP 0x0000001F #define DPORT_PRO_UART_INTR_MAP_S 0 #define PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) #define DPORT_PRO_UART1_INTR_MAP 0x0000001F #define DPORT_PRO_UART1_INTR_MAP_S 0 #define PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) #define DPORT_PRO_UART2_INTR_MAP 0x0000001F #define DPORT_PRO_UART2_INTR_MAP_S 0 #define PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 #define PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) #define DPORT_PRO_EMAC_INT_MAP 0x0000001F #define DPORT_PRO_EMAC_INT_MAP_S 0 #define PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) #define DPORT_PRO_PWM0_INTR_MAP 0x0000001F #define DPORT_PRO_PWM0_INTR_MAP_S 0 #define PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) #define DPORT_PRO_PWM1_INTR_MAP 0x0000001F #define DPORT_PRO_PWM1_INTR_MAP_S 0 #define PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) #define DPORT_PRO_PWM2_INTR_MAP 0x0000001F #define DPORT_PRO_PWM2_INTR_MAP_S 0 #define PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) #define DPORT_PRO_PWM3_INTR_MAP 0x0000001F #define DPORT_PRO_PWM3_INTR_MAP_S 0 #define PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) #define DPORT_PRO_LEDC_INT_MAP 0x0000001F #define DPORT_PRO_LEDC_INT_MAP_S 0 #define PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) #define DPORT_PRO_EFUSE_INT_MAP 0x0000001F #define DPORT_PRO_EFUSE_INT_MAP_S 0 #define PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) #define DPORT_PRO_CAN_INT_MAP 0x0000001F #define DPORT_PRO_CAN_INT_MAP_S 0 #define PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) #define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F #define DPORT_PRO_RTC_CORE_INTR_MAP_S 0 #define PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) #define DPORT_PRO_RMT_INTR_MAP 0x0000001F #define DPORT_PRO_RMT_INTR_MAP_S 0 #define PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) #define DPORT_PRO_PCNT_INTR_MAP 0x0000001F #define DPORT_PRO_PCNT_INTR_MAP_S 0 #define PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) #define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F #define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 #define PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) #define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F #define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 #define PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) #define DPORT_PRO_RSA_INTR_MAP 0x0000001F #define DPORT_PRO_RSA_INTR_MAP_S 0 #define PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) #define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F #define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 #define PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) #define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F #define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 #define PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) #define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F #define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 #define PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) #define DPORT_PRO_WDG_INT_MAP 0x0000001F #define DPORT_PRO_WDG_INT_MAP_S 0 #define PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) #define DPORT_PRO_TIMER_INT1_MAP 0x0000001F #define DPORT_PRO_TIMER_INT1_MAP_S 0 #define PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) #define DPORT_PRO_TIMER_INT2_MAP 0x0000001F #define DPORT_PRO_TIMER_INT2_MAP_S 0 #define PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) #define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 #define PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) #define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 #define PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) #define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 #define PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) #define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 #define PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) #define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 #define PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) #define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 #define PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 #define PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 #define PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) #define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F #define DPORT_PRO_MMU_IA_INT_MAP_S 0 #define PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) #define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F #define DPORT_PRO_MPU_IA_INT_MAP_S 0 #define PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) #define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F #define DPORT_PRO_CACHE_IA_INT_MAP_S 0 #define APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) #define DPORT_APP_MAC_INTR_MAP 0x0000001F #define DPORT_APP_MAC_INTR_MAP_S 0 #define APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) #define DPORT_APP_MAC_NMI_MAP 0x0000001F #define DPORT_APP_MAC_NMI_MAP_S 0 #define APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) #define DPORT_APP_BB_INT_MAP 0x0000001F #define DPORT_APP_BB_INT_MAP_S 0 #define APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) #define DPORT_APP_BT_MAC_INT_MAP 0x0000001F #define DPORT_APP_BT_MAC_INT_MAP_S 0 #define APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) #define DPORT_APP_BT_BB_INT_MAP 0x0000001F #define DPORT_APP_BT_BB_INT_MAP_S 0 #define APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) #define DPORT_APP_BT_BB_NMI_MAP 0x0000001F #define DPORT_APP_BT_BB_NMI_MAP_S 0 #define APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) #define DPORT_APP_RWBT_IRQ_MAP 0x0000001F #define DPORT_APP_RWBT_IRQ_MAP_S 0 #define APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) #define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F #define DPORT_APP_RWBLE_IRQ_MAP_S 0 #define APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) #define DPORT_APP_RWBT_NMI_MAP 0x0000001F #define DPORT_APP_RWBT_NMI_MAP_S 0 #define APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) #define DPORT_APP_RWBLE_NMI_MAP 0x0000001F #define DPORT_APP_RWBLE_NMI_MAP_S 0 #define APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) #define DPORT_APP_SLC0_INTR_MAP 0x0000001F #define DPORT_APP_SLC0_INTR_MAP_S 0 #define APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) #define DPORT_APP_SLC1_INTR_MAP 0x0000001F #define DPORT_APP_SLC1_INTR_MAP_S 0 #define APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) #define DPORT_APP_UHCI0_INTR_MAP 0x0000001F #define DPORT_APP_UHCI0_INTR_MAP_S 0 #define APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) #define DPORT_APP_UHCI1_INTR_MAP 0x0000001F #define DPORT_APP_UHCI1_INTR_MAP_S 0 #define APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) #define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 #define APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) #define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 #define APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) #define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 #define APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) #define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 #define APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) #define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 #define APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) #define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 #define APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 #define APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 #define APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) #define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 #define APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 #define APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 #define APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 #define APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 #define APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 #define APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) #define DPORT_APP_SPI_INTR_0_MAP 0x0000001F #define DPORT_APP_SPI_INTR_0_MAP_S 0 #define APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) #define DPORT_APP_SPI_INTR_1_MAP 0x0000001F #define DPORT_APP_SPI_INTR_1_MAP_S 0 #define APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) #define DPORT_APP_SPI_INTR_2_MAP 0x0000001F #define DPORT_APP_SPI_INTR_2_MAP_S 0 #define APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) #define DPORT_APP_SPI_INTR_3_MAP 0x0000001F #define DPORT_APP_SPI_INTR_3_MAP_S 0 #define APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) #define DPORT_APP_I2S0_INT_MAP 0x0000001F #define DPORT_APP_I2S0_INT_MAP_S 0 #define APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) #define DPORT_APP_I2S1_INT_MAP 0x0000001F #define DPORT_APP_I2S1_INT_MAP_S 0 #define APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) #define DPORT_APP_UART_INTR_MAP 0x0000001F #define DPORT_APP_UART_INTR_MAP_S 0 #define APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) #define DPORT_APP_UART1_INTR_MAP 0x0000001F #define DPORT_APP_UART1_INTR_MAP_S 0 #define APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) #define DPORT_APP_UART2_INTR_MAP 0x0000001F #define DPORT_APP_UART2_INTR_MAP_S 0 #define APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 #define APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) #define DPORT_APP_EMAC_INT_MAP 0x0000001F #define DPORT_APP_EMAC_INT_MAP_S 0 #define APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) #define DPORT_APP_PWM0_INTR_MAP 0x0000001F #define DPORT_APP_PWM0_INTR_MAP_S 0 #define APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) #define DPORT_APP_PWM1_INTR_MAP 0x0000001F #define DPORT_APP_PWM1_INTR_MAP_S 0 #define APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) #define DPORT_APP_PWM2_INTR_MAP 0x0000001F #define DPORT_APP_PWM2_INTR_MAP_S 0 #define APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) #define DPORT_APP_PWM3_INTR_MAP 0x0000001F #define DPORT_APP_PWM3_INTR_MAP_S 0 #define APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) #define DPORT_APP_LEDC_INT_MAP 0x0000001F #define DPORT_APP_LEDC_INT_MAP_S 0 #define APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) #define DPORT_APP_EFUSE_INT_MAP 0x0000001F #define DPORT_APP_EFUSE_INT_MAP_S 0 #define APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) #define DPORT_APP_CAN_INT_MAP 0x0000001F #define DPORT_APP_CAN_INT_MAP_S 0 #define APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) #define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F #define DPORT_APP_RTC_CORE_INTR_MAP_S 0 #define APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) #define DPORT_APP_RMT_INTR_MAP 0x0000001F #define DPORT_APP_RMT_INTR_MAP_S 0 #define APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) #define DPORT_APP_PCNT_INTR_MAP 0x0000001F #define DPORT_APP_PCNT_INTR_MAP_S 0 #define APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) #define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F #define DPORT_APP_I2C_EXT0_INTR_MAP_S 0 #define APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) #define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F #define DPORT_APP_I2C_EXT1_INTR_MAP_S 0 #define APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) #define DPORT_APP_RSA_INTR_MAP 0x0000001F #define DPORT_APP_RSA_INTR_MAP_S 0 #define APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) #define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F #define DPORT_APP_SPI1_DMA_INT_MAP_S 0 #define APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) #define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F #define DPORT_APP_SPI2_DMA_INT_MAP_S 0 #define APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) #define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F #define DPORT_APP_SPI3_DMA_INT_MAP_S 0 #define APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) #define DPORT_APP_WDG_INT_MAP 0x0000001F #define DPORT_APP_WDG_INT_MAP_S 0 #define APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) #define DPORT_APP_TIMER_INT1_MAP 0x0000001F #define DPORT_APP_TIMER_INT1_MAP_S 0 #define APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) #define DPORT_APP_TIMER_INT2_MAP 0x0000001F #define DPORT_APP_TIMER_INT2_MAP_S 0 #define APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) #define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 #define APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) #define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 #define APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) #define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 #define APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) #define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 #define APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) #define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 #define APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) #define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 #define APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) #define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 #define APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) #define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 #define APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) #define DPORT_APP_MMU_IA_INT_MAP 0x0000001F #define DPORT_APP_MMU_IA_INT_MAP_S 0 #define APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) #define DPORT_APP_MPU_IA_INT_MAP 0x0000001F #define DPORT_APP_MPU_IA_INT_MAP_S 0 #define APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) #define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F #define DPORT_APP_CACHE_IA_INT_MAP_S 0 #define AHBLITE_MPU_TABLE_UART (DR_REG_DPORT_BASE + 0x32C) #define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UART_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_SPI1 (DR_REG_DPORT_BASE + 0x330) #define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_SPI0 (DR_REG_DPORT_BASE + 0x334) #define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_GPIO (DR_REG_DPORT_BASE + 0x338) #define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_FE2 (DR_REG_DPORT_BASE + 0x33C) #define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_FE (DR_REG_DPORT_BASE + 0x340) #define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_FE_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_TIMER (DR_REG_DPORT_BASE + 0x344) #define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_RTC (DR_REG_DPORT_BASE + 0x348) #define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_IO_MUX (DR_REG_DPORT_BASE + 0x34C) #define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_WDG (DR_REG_DPORT_BASE + 0x350) #define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_HINF (DR_REG_DPORT_BASE + 0x354) #define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_UHCI1 (DR_REG_DPORT_BASE + 0x358) #define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_MISC (DR_REG_DPORT_BASE + 0x35C) #define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_I2C (DR_REG_DPORT_BASE + 0x360) #define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_I2S0 (DR_REG_DPORT_BASE + 0x364) #define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_UART1 (DR_REG_DPORT_BASE + 0x368) #define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_BT (DR_REG_DPORT_BASE + 0x36C) #define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_BT_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_BT_BUFFER (DR_REG_DPORT_BASE + 0x370) #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_I2C_EXT0 (DR_REG_DPORT_BASE + 0x374) #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_UHCI0 (DR_REG_DPORT_BASE + 0x378) #define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_SLCHOST (DR_REG_DPORT_BASE + 0x37C) #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_RMT (DR_REG_DPORT_BASE + 0x380) #define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_PCNT (DR_REG_DPORT_BASE + 0x384) #define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_SLC (DR_REG_DPORT_BASE + 0x388) #define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_LEDC (DR_REG_DPORT_BASE + 0x38C) #define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_EFUSE (DR_REG_DPORT_BASE + 0x390) #define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_SPI_ENCRYPT (DR_REG_DPORT_BASE + 0x394) #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_BB (DR_REG_DPORT_BASE + 0x398) #define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_BB_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_PWM0 (DR_REG_DPORT_BASE + 0x39C) #define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_TIMERGROUP (DR_REG_DPORT_BASE + 0x3A0) #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_TIMERGROUP1 (DR_REG_DPORT_BASE + 0x3A4) #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_SPI2 (DR_REG_DPORT_BASE + 0x3A8) #define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_SPI3 (DR_REG_DPORT_BASE + 0x3AC) #define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_APB_CTRL (DR_REG_DPORT_BASE + 0x3B0) #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_I2C_EXT1 (DR_REG_DPORT_BASE + 0x3B4) #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_SDIO_HOST (DR_REG_DPORT_BASE + 0x3B8) #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_EMAC (DR_REG_DPORT_BASE + 0x3BC) #define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_CAN (DR_REG_DPORT_BASE + 0x3C0) #define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_PWM1 (DR_REG_DPORT_BASE + 0x3C4) #define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_I2S1 (DR_REG_DPORT_BASE + 0x3C8) #define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_UART2 (DR_REG_DPORT_BASE + 0x3CC) #define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_PWM2 (DR_REG_DPORT_BASE + 0x3D0) #define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_PWM3 (DR_REG_DPORT_BASE + 0x3D4) #define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_RWBT (DR_REG_DPORT_BASE + 0x3D8) #define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_BTMAC (DR_REG_DPORT_BASE + 0x3DC) #define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_WIFIMAC (DR_REG_DPORT_BASE + 0x3E0) #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 #define AHBLITE_MPU_TABLE_PWR (DR_REG_DPORT_BASE + 0x3E4) #define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 #define MEM_ACCESS_DBUG0 (DR_REG_DPORT_BASE + 0x3E8) #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 #define DPORT_INTERNAL_SRAM_IA 0x00000FFF #define DPORT_INTERNAL_SRAM_IA_S 14 #define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F #define DPORT_INTERNAL_SRAM_MMU_AD_S 10 #define DPORT_SHARE_ROM_IA 0x0000000F #define DPORT_SHARE_ROM_IA_S 6 #define DPORT_SHARE_ROM_MPU_AD 0x00000003 #define DPORT_SHARE_ROM_MPU_AD_S 4 #define DPORT_APP_ROM_IA (BIT(3)) #define DPORT_APP_ROM_IA_S 3 #define DPORT_APP_ROM_MPU_AD (BIT(2)) #define DPORT_APP_ROM_MPU_AD_S 2 #define DPORT_PRO_ROM_IA (BIT(1)) #define DPORT_PRO_ROM_IA_S 1 #define DPORT_PRO_ROM_MPU_AD (BIT(0)) #define DPORT_PRO_ROM_MPU_AD_S 0 #define MEM_ACCESS_DBUG1 (DR_REG_DPORT_BASE + 0x3EC) #define DPORT_AHBLITE_IA (BIT(10)) #define DPORT_AHBLITE_IA_S 10 #define DPORT_AHBLITE_ACCESS_DENY (BIT(9)) #define DPORT_AHBLITE_ACCESS_DENY_S 9 #define DPORT_AHB_ACCESS_DENY (BIT(8)) #define DPORT_AHB_ACCESS_DENY_S 8 #define DPORT_DPORT_PIDGEN_IA 0x00000003 #define DPORT_DPORT_PIDGEN_IA_S 6 #define DPORT_DPORT_ARB_IA 0x00000003 #define DPORT_DPORT_ARB_IA_S 4 #define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F #define DPORT_INTERNAL_SRAM_MMU_MISS_S 0 #define PRO_DCACHE_DBUG_REG0 (DR_REG_DPORT_BASE + 0x3F0) #define DPORT_PRO_RX_END (BIT(23)) #define DPORT_PRO_RX_END_S 23 #define DPORT_PRO_SLAVE_WDATA_V (BIT(22)) #define DPORT_PRO_SLAVE_WDATA_V_S 22 #define DPORT_PRO_SLAVE_WR (BIT(21)) #define DPORT_PRO_SLAVE_WR_S 21 #define DPORT_PRO_TX_END (BIT(20)) #define DPORT_PRO_TX_END_S 20 #define DPORT_PRO_WR_BAK_TO_READ (BIT(19)) #define DPORT_PRO_WR_BAK_TO_READ_S 19 #define DPORT_PRO_CACHE_STATE 0x00000FFF #define DPORT_PRO_CACHE_STATE_S 7 #define DPORT_PRO_CACHE_IA 0x0000003F #define DPORT_PRO_CACHE_IA_S 1 #define DPORT_PRO_CACHE_MMU_IA (BIT(0)) #define DPORT_PRO_CACHE_MMU_IA_S 0 #define PRO_DCACHE_DBUG_REG1 (DR_REG_DPORT_BASE + 0x3F4) #define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF #define DPORT_PRO_CTAG_RAM_RDATA_S 0 #define PRO_DCACHE_DBUG_REG2 (DR_REG_DPORT_BASE + 0x3F8) #define DPORT_PRO_CACHE_VADDR 0x07FFFFFF #define DPORT_PRO_CACHE_VADDR_S 0 #define PRO_DCACHE_DBUG_REG3 (DR_REG_DPORT_BASE + 0x3FC) #define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 #define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F #define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 #define DPORT_PRO_MMU_RDATA 0x000001FF #define DPORT_PRO_MMU_RDATA_S 0 #define PRO_DCACHE_DBUG_REG4 (DR_REG_DPORT_BASE + 0x400) #define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF #define DPORT_PRO_DRAM1ADDR0_IA_S 0 #define PRO_DCACHE_DBUG_REG5 (DR_REG_DPORT_BASE + 0x404) #define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF #define DPORT_PRO_DROM0ADDR0_IA_S 0 #define PRO_DCACHE_DBUG_REG6 (DR_REG_DPORT_BASE + 0x408) #define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF #define DPORT_PRO_IRAM0ADDR_IA_S 0 #define PRO_DCACHE_DBUG_REG7 (DR_REG_DPORT_BASE + 0x40C) #define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF #define DPORT_PRO_IRAM1ADDR_IA_S 0 #define PRO_DCACHE_DBUG_REG8 (DR_REG_DPORT_BASE + 0x410) #define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF #define DPORT_PRO_IROM0ADDR_IA_S 0 #define PRO_DCACHE_DBUG_REG9 (DR_REG_DPORT_BASE + 0x414) #define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF #define DPORT_PRO_OPSDRAMADDR_IA_S 0 #define APP_DCACHE_DBUG_REG0 (DR_REG_DPORT_BASE + 0x418) #define DPORT_APP_RX_END (BIT(23)) #define DPORT_APP_RX_END_S 23 #define DPORT_APP_SLAVE_WDATA_V (BIT(22)) #define DPORT_APP_SLAVE_WDATA_V_S 22 #define DPORT_APP_SLAVE_WR (BIT(21)) #define DPORT_APP_SLAVE_WR_S 21 #define DPORT_APP_TX_END (BIT(20)) #define DPORT_APP_TX_END_S 20 #define DPORT_APP_WR_BAK_TO_READ (BIT(19)) #define DPORT_APP_WR_BAK_TO_READ_S 19 #define DPORT_APP_CACHE_STATE 0x00000FFF #define DPORT_APP_CACHE_STATE_S 7 #define DPORT_APP_CACHE_IA 0x0000003F #define DPORT_APP_CACHE_IA_S 1 #define DPORT_APP_CACHE_MMU_IA (BIT(0)) #define DPORT_APP_CACHE_MMU_IA_S 0 #define APP_DCACHE_DBUG_REG1 (DR_REG_DPORT_BASE + 0x41C) #define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF #define DPORT_APP_CTAG_RAM_RDATA_S 0 #define APP_DCACHE_DBUG_REG2 (DR_REG_DPORT_BASE + 0x420) #define DPORT_APP_CACHE_VADDR 0x07FFFFFF #define DPORT_APP_CACHE_VADDR_S 0 #define APP_DCACHE_DBUG_REG3 (DR_REG_DPORT_BASE + 0x424) #define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) #define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 #define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F #define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 #define DPORT_APP_MMU_RDATA 0x000001FF #define DPORT_APP_MMU_RDATA_S 0 #define APP_DCACHE_DBUG_REG4 (DR_REG_DPORT_BASE + 0x428) #define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF #define DPORT_APP_DRAM1ADDR0_IA_S 0 #define APP_DCACHE_DBUG_REG5 (DR_REG_DPORT_BASE + 0x42C) #define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF #define DPORT_APP_DROM0ADDR0_IA_S 0 #define APP_DCACHE_DBUG_REG6 (DR_REG_DPORT_BASE + 0x430) #define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF #define DPORT_APP_IRAM0ADDR_IA_S 0 #define APP_DCACHE_DBUG_REG7 (DR_REG_DPORT_BASE + 0x434) #define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF #define DPORT_APP_IRAM1ADDR_IA_S 0 #define APP_DCACHE_DBUG_REG8 (DR_REG_DPORT_BASE + 0x438) #define DPORT_APP_IROM0ADDR_IA 0x000FFFFF #define DPORT_APP_IROM0ADDR_IA_S 0 #define APP_DCACHE_DBUG_REG9 (DR_REG_DPORT_BASE + 0x43C) #define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF #define DPORT_APP_OPSDRAMADDR_IA_S 0 #define PRO_CPU_RECORD_CTRL (DR_REG_DPORT_BASE + 0x440) #define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) #define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 #define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) #define DPORT_PRO_CPU_RECORD_DISABLE_S 4 #define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) #define DPORT_PRO_CPU_RECORD_ENABLE_S 0 #define PRO_CPU_RECORD_STATUS (DR_REG_DPORT_BASE + 0x444) #define DPORT_PRO_CPU_RECORDING (BIT(0)) #define DPORT_PRO_CPU_RECORDING_S 0 #define PRO_CPU_RECORD_PID (DR_REG_DPORT_BASE + 0x448) #define DPORT_RECORD_PRO_PID 0x00000007 #define DPORT_RECORD_PRO_PID_S 0 #define PRO_CPU_RECORD_PDEBUGINST (DR_REG_DPORT_BASE + 0x44C) #define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGINST_S 0 #define PRO_CPU_RECORD_PDEBUGSTATUS (DR_REG_DPORT_BASE + 0x450) #define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF #define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 #define PRO_CPU_RECORD_PDEBUGDATA (DR_REG_DPORT_BASE + 0x454) #define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGDATA_S 0 #define PRO_CPU_RECORD_PDEBUGPC (DR_REG_DPORT_BASE + 0x458) #define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGPC_S 0 #define PRO_CPU_RECORD_PDEBUGLS0STAT (DR_REG_DPORT_BASE + 0x45C) #define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 #define PRO_CPU_RECORD_PDEBUGLS0ADDR (DR_REG_DPORT_BASE + 0x460) #define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 #define PRO_CPU_RECORD_PDEBUGLS0DATA (DR_REG_DPORT_BASE + 0x464) #define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 #define APP_CPU_RECORD_CTRL (DR_REG_DPORT_BASE + 0x468) #define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) #define DPORT_APP_CPU_PDEBUG_ENABLE_S 8 #define DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) #define DPORT_APP_CPU_RECORD_DISABLE_S 4 #define DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) #define DPORT_APP_CPU_RECORD_ENABLE_S 0 #define APP_CPU_RECORD_STATUS (DR_REG_DPORT_BASE + 0x46C) #define DPORT_APP_CPU_RECORDING (BIT(0)) #define DPORT_APP_CPU_RECORDING_S 0 #define APP_CPU_RECORD_PID (DR_REG_DPORT_BASE + 0x470) #define DPORT_RECORD_APP_PID 0x00000007 #define DPORT_RECORD_APP_PID_S 0 #define APP_CPU_RECORD_PDEBUGINST (DR_REG_DPORT_BASE + 0x474) #define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGINST_S 0 #define APP_CPU_RECORD_PDEBUGSTATUS (DR_REG_DPORT_BASE + 0x478) #define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF #define DPORT_RECORD_APP_PDEBUGSTATUS_S 0 #define APP_CPU_RECORD_PDEBUGDATA (DR_REG_DPORT_BASE + 0x47C) #define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGDATA_S 0 #define APP_CPU_RECORD_PDEBUGPC (DR_REG_DPORT_BASE + 0x480) #define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGPC_S 0 #define APP_CPU_RECORD_PDEBUGLS0STAT (DR_REG_DPORT_BASE + 0x484) #define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 #define APP_CPU_RECORD_PDEBUGLS0ADDR (DR_REG_DPORT_BASE + 0x488) #define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 #define APP_CPU_RECORD_PDEBUGLS0DATA (DR_REG_DPORT_BASE + 0x48C) #define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 #define RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) #define DPORT_RSA_PD (BIT(0)) #define DPORT_RSA_PD_S 0 #define ROM_MPU_TABLE0 (DR_REG_DPORT_BASE + 0x494) #define DPORT_ROM_MPU_TABLE0 0x00000003 #define DPORT_ROM_MPU_TABLE0_S 0 #define ROM_MPU_TABLE1 (DR_REG_DPORT_BASE + 0x498) #define DPORT_ROM_MPU_TABLE1 0x00000003 #define DPORT_ROM_MPU_TABLE1_S 0 #define ROM_MPU_TABLE2 (DR_REG_DPORT_BASE + 0x49C) #define DPORT_ROM_MPU_TABLE2 0x00000003 #define DPORT_ROM_MPU_TABLE2_S 0 #define ROM_MPU_TABLE3 (DR_REG_DPORT_BASE + 0x4A0) #define DPORT_ROM_MPU_TABLE3 0x00000003 #define DPORT_ROM_MPU_TABLE3_S 0 #define SHROM_MPU_TABLE0 (DR_REG_DPORT_BASE + 0x4A4) #define DPORT_SHROM_MPU_TABLE0 0x00000003 #define DPORT_SHROM_MPU_TABLE0_S 0 #define SHROM_MPU_TABLE1 (DR_REG_DPORT_BASE + 0x4A8) #define DPORT_SHROM_MPU_TABLE1 0x00000003 #define DPORT_SHROM_MPU_TABLE1_S 0 #define SHROM_MPU_TABLE2 (DR_REG_DPORT_BASE + 0x4AC) #define DPORT_SHROM_MPU_TABLE2 0x00000003 #define DPORT_SHROM_MPU_TABLE2_S 0 #define SHROM_MPU_TABLE3 (DR_REG_DPORT_BASE + 0x4B0) #define DPORT_SHROM_MPU_TABLE3 0x00000003 #define DPORT_SHROM_MPU_TABLE3_S 0 #define SHROM_MPU_TABLE4 (DR_REG_DPORT_BASE + 0x4B4) #define DPORT_SHROM_MPU_TABLE4 0x00000003 #define DPORT_SHROM_MPU_TABLE4_S 0 #define SHROM_MPU_TABLE5 (DR_REG_DPORT_BASE + 0x4B8) #define DPORT_SHROM_MPU_TABLE5 0x00000003 #define DPORT_SHROM_MPU_TABLE5_S 0 #define SHROM_MPU_TABLE6 (DR_REG_DPORT_BASE + 0x4BC) #define DPORT_SHROM_MPU_TABLE6 0x00000003 #define DPORT_SHROM_MPU_TABLE6_S 0 #define SHROM_MPU_TABLE7 (DR_REG_DPORT_BASE + 0x4C0) #define DPORT_SHROM_MPU_TABLE7 0x00000003 #define DPORT_SHROM_MPU_TABLE7_S 0 #define SHROM_MPU_TABLE8 (DR_REG_DPORT_BASE + 0x4C4) #define DPORT_SHROM_MPU_TABLE8 0x00000003 #define DPORT_SHROM_MPU_TABLE8_S 0 #define SHROM_MPU_TABLE9 (DR_REG_DPORT_BASE + 0x4C8) #define DPORT_SHROM_MPU_TABLE9 0x00000003 #define DPORT_SHROM_MPU_TABLE9_S 0 #define SHROM_MPU_TABLE10 (DR_REG_DPORT_BASE + 0x4CC) #define DPORT_SHROM_MPU_TABLE10 0x00000003 #define DPORT_SHROM_MPU_TABLE10_S 0 #define SHROM_MPU_TABLE11 (DR_REG_DPORT_BASE + 0x4D0) #define DPORT_SHROM_MPU_TABLE11 0x00000003 #define DPORT_SHROM_MPU_TABLE11_S 0 #define SHROM_MPU_TABLE12 (DR_REG_DPORT_BASE + 0x4D4) #define DPORT_SHROM_MPU_TABLE12 0x00000003 #define DPORT_SHROM_MPU_TABLE12_S 0 #define SHROM_MPU_TABLE13 (DR_REG_DPORT_BASE + 0x4D8) #define DPORT_SHROM_MPU_TABLE13 0x00000003 #define DPORT_SHROM_MPU_TABLE13_S 0 #define SHROM_MPU_TABLE14 (DR_REG_DPORT_BASE + 0x4DC) #define DPORT_SHROM_MPU_TABLE14 0x00000003 #define DPORT_SHROM_MPU_TABLE14_S 0 #define SHROM_MPU_TABLE15 (DR_REG_DPORT_BASE + 0x4E0) #define DPORT_SHROM_MPU_TABLE15 0x00000003 #define DPORT_SHROM_MPU_TABLE15_S 0 #define SHROM_MPU_TABLE16 (DR_REG_DPORT_BASE + 0x4E4) #define DPORT_SHROM_MPU_TABLE16 0x00000003 #define DPORT_SHROM_MPU_TABLE16_S 0 #define SHROM_MPU_TABLE17 (DR_REG_DPORT_BASE + 0x4E8) #define DPORT_SHROM_MPU_TABLE17 0x00000003 #define DPORT_SHROM_MPU_TABLE17_S 0 #define SHROM_MPU_TABLE18 (DR_REG_DPORT_BASE + 0x4EC) #define DPORT_SHROM_MPU_TABLE18 0x00000003 #define DPORT_SHROM_MPU_TABLE18_S 0 #define SHROM_MPU_TABLE19 (DR_REG_DPORT_BASE + 0x4F0) #define DPORT_SHROM_MPU_TABLE19 0x00000003 #define DPORT_SHROM_MPU_TABLE19_S 0 #define SHROM_MPU_TABLE20 (DR_REG_DPORT_BASE + 0x4F4) #define DPORT_SHROM_MPU_TABLE20 0x00000003 #define DPORT_SHROM_MPU_TABLE20_S 0 #define SHROM_MPU_TABLE21 (DR_REG_DPORT_BASE + 0x4F8) #define DPORT_SHROM_MPU_TABLE21 0x00000003 #define DPORT_SHROM_MPU_TABLE21_S 0 #define SHROM_MPU_TABLE22 (DR_REG_DPORT_BASE + 0x4FC) #define DPORT_SHROM_MPU_TABLE22 0x00000003 #define DPORT_SHROM_MPU_TABLE22_S 0 #define SHROM_MPU_TABLE23 (DR_REG_DPORT_BASE + 0x500) #define DPORT_SHROM_MPU_TABLE23 0x00000003 #define DPORT_SHROM_MPU_TABLE23_S 0 #define IMMU_TABLE0 (DR_REG_DPORT_BASE + 0x504) #define DPORT_IMMU_TABLE0 0x0000007F #define DPORT_IMMU_TABLE0_S 0 #define IMMU_TABLE1 (DR_REG_DPORT_BASE + 0x508) #define DPORT_IMMU_TABLE1 0x0000007F #define DPORT_IMMU_TABLE1_S 0 #define IMMU_TABLE2 (DR_REG_DPORT_BASE + 0x50C) #define DPORT_IMMU_TABLE2 0x0000007F #define DPORT_IMMU_TABLE2_S 0 #define IMMU_TABLE3 (DR_REG_DPORT_BASE + 0x510) #define DPORT_IMMU_TABLE3 0x0000007F #define DPORT_IMMU_TABLE3_S 0 #define IMMU_TABLE4 (DR_REG_DPORT_BASE + 0x514) #define DPORT_IMMU_TABLE4 0x0000007F #define DPORT_IMMU_TABLE4_S 0 #define IMMU_TABLE5 (DR_REG_DPORT_BASE + 0x518) #define DPORT_IMMU_TABLE5 0x0000007F #define DPORT_IMMU_TABLE5_S 0 #define IMMU_TABLE6 (DR_REG_DPORT_BASE + 0x51C) #define DPORT_IMMU_TABLE6 0x0000007F #define DPORT_IMMU_TABLE6_S 0 #define IMMU_TABLE7 (DR_REG_DPORT_BASE + 0x520) #define DPORT_IMMU_TABLE7 0x0000007F #define DPORT_IMMU_TABLE7_S 0 #define IMMU_TABLE8 (DR_REG_DPORT_BASE + 0x524) #define DPORT_IMMU_TABLE8 0x0000007F #define DPORT_IMMU_TABLE8_S 0 #define IMMU_TABLE9 (DR_REG_DPORT_BASE + 0x528) #define DPORT_IMMU_TABLE9 0x0000007F #define DPORT_IMMU_TABLE9_S 0 #define IMMU_TABLE10 (DR_REG_DPORT_BASE + 0x52C) #define DPORT_IMMU_TABLE10 0x0000007F #define DPORT_IMMU_TABLE10_S 0 #define IMMU_TABLE11 (DR_REG_DPORT_BASE + 0x530) #define DPORT_IMMU_TABLE11 0x0000007F #define DPORT_IMMU_TABLE11_S 0 #define IMMU_TABLE12 (DR_REG_DPORT_BASE + 0x534) #define DPORT_IMMU_TABLE12 0x0000007F #define DPORT_IMMU_TABLE12_S 0 #define IMMU_TABLE13 (DR_REG_DPORT_BASE + 0x538) #define DPORT_IMMU_TABLE13 0x0000007F #define DPORT_IMMU_TABLE13_S 0 #define IMMU_TABLE14 (DR_REG_DPORT_BASE + 0x53C) #define DPORT_IMMU_TABLE14 0x0000007F #define DPORT_IMMU_TABLE14_S 0 #define IMMU_TABLE15 (DR_REG_DPORT_BASE + 0x540) #define DPORT_IMMU_TABLE15 0x0000007F #define DPORT_IMMU_TABLE15_S 0 #define DMMU_TABLE0 (DR_REG_DPORT_BASE + 0x544) #define DPORT_DMMU_TABLE0 0x0000007F #define DPORT_DMMU_TABLE0_S 0 #define DMMU_TABLE1 (DR_REG_DPORT_BASE + 0x548) #define DPORT_DMMU_TABLE1 0x0000007F #define DPORT_DMMU_TABLE1_S 0 #define DMMU_TABLE2 (DR_REG_DPORT_BASE + 0x54C) #define DPORT_DMMU_TABLE2 0x0000007F #define DPORT_DMMU_TABLE2_S 0 #define DMMU_TABLE3 (DR_REG_DPORT_BASE + 0x550) #define DPORT_DMMU_TABLE3 0x0000007F #define DPORT_DMMU_TABLE3_S 0 #define DMMU_TABLE4 (DR_REG_DPORT_BASE + 0x554) #define DPORT_DMMU_TABLE4 0x0000007F #define DPORT_DMMU_TABLE4_S 0 #define DMMU_TABLE5 (DR_REG_DPORT_BASE + 0x558) #define DPORT_DMMU_TABLE5 0x0000007F #define DPORT_DMMU_TABLE5_S 0 #define DMMU_TABLE6 (DR_REG_DPORT_BASE + 0x55C) #define DPORT_DMMU_TABLE6 0x0000007F #define DPORT_DMMU_TABLE6_S 0 #define DMMU_TABLE7 (DR_REG_DPORT_BASE + 0x560) #define DPORT_DMMU_TABLE7 0x0000007F #define DPORT_DMMU_TABLE7_S 0 #define DMMU_TABLE8 (DR_REG_DPORT_BASE + 0x564) #define DPORT_DMMU_TABLE8 0x0000007F #define DPORT_DMMU_TABLE8_S 0 #define DMMU_TABLE9 (DR_REG_DPORT_BASE + 0x568) #define DPORT_DMMU_TABLE9 0x0000007F #define DPORT_DMMU_TABLE9_S 0 #define DMMU_TABLE10 (DR_REG_DPORT_BASE + 0x56C) #define DPORT_DMMU_TABLE10 0x0000007F #define DPORT_DMMU_TABLE10_S 0 #define DMMU_TABLE11 (DR_REG_DPORT_BASE + 0x570) #define DPORT_DMMU_TABLE11 0x0000007F #define DPORT_DMMU_TABLE11_S 0 #define DMMU_TABLE12 (DR_REG_DPORT_BASE + 0x574) #define DPORT_DMMU_TABLE12 0x0000007F #define DPORT_DMMU_TABLE12_S 0 #define DMMU_TABLE13 (DR_REG_DPORT_BASE + 0x578) #define DPORT_DMMU_TABLE13 0x0000007F #define DPORT_DMMU_TABLE13_S 0 #define DMMU_TABLE14 (DR_REG_DPORT_BASE + 0x57C) #define DPORT_DMMU_TABLE14 0x0000007F #define DPORT_DMMU_TABLE14_S 0 #define DMMU_TABLE15 (DR_REG_DPORT_BASE + 0x580) #define DPORT_DMMU_TABLE15 0x0000007F #define DPORT_DMMU_TABLE15_S 0 #define PRO_INTRUSION_CTRL (DR_REG_DPORT_BASE + 0x584) #define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) #define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 #define PRO_INTRUSION_STATUS (DR_REG_DPORT_BASE + 0x588) #define DPORT_PRO_INTRUSION_RECORD 0x0000000F #define DPORT_PRO_INTRUSION_RECORD_S 0 #define APP_INTRUSION_CTRL (DR_REG_DPORT_BASE + 0x58C) #define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) #define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 #define APP_INTRUSION_STATUS (DR_REG_DPORT_BASE + 0x590) #define DPORT_APP_INTRUSION_RECORD 0x0000000F #define DPORT_APP_INTRUSION_RECORD_S 0 #define FRONT_END_MEM_PD (DR_REG_DPORT_BASE + 0x594) #define DPORT_PBUS_MEM_FORCE_PD (BIT(3)) #define DPORT_PBUS_MEM_FORCE_PD_S 3 #define DPORT_PBUS_MEM_FORCE_PU (BIT(2)) #define DPORT_PBUS_MEM_FORCE_PU_S 2 #define DPORT_AGC_MEM_FORCE_PD (BIT(1)) #define DPORT_AGC_MEM_FORCE_PD_S 1 #define DPORT_AGC_MEM_FORCE_PU (BIT(0)) #define DPORT_AGC_MEM_FORCE_PU_S 0 #define MMU_IA_INT_EN (DR_REG_DPORT_BASE + 0x598) #define DPORT_MMU_IA_INT_EN 0x00FFFFFF #define DPORT_MMU_IA_INT_EN_S 0 #define MPU_IA_INT_EN (DR_REG_DPORT_BASE + 0x59C) #define DPORT_MPU_IA_INT_EN 0x0001FFFF #define DPORT_MPU_IA_INT_EN_S 0 #define CACHE_IA_INT_EN (DR_REG_DPORT_BASE + 0x5A0) #define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF #define DPORT_CACHE_IA_INT_EN_S 0 #define SECURE_BOOT_CTRL (DR_REG_DPORT_BASE + 0x5A4) #define DPORT_SW_BOOTLOADER_SEL (BIT(0)) #define DPORT_SW_BOOTLOADER_SEL_S 0 #define SPI_DMA_CHAN_SEL (DR_REG_DPORT_BASE + 0x5A8) #define DPORT_SPI3_DMA_CHAN_SEL 0x00000003 #define DPORT_SPI3_DMA_CHAN_SEL_S 4 #define DPORT_SPI2_DMA_CHAN_SEL 0x00000003 #define DPORT_SPI2_DMA_CHAN_SEL_S 2 #define DPORT_SPI1_DMA_CHAN_SEL 0x00000003 #define DPORT_SPI1_DMA_CHAN_SEL_S 0 #define PRO_VECBASE_CTRL (DR_REG_DPORT_BASE + 0x5AC) #define DPORT_PRO_OUT_VECBASE_SEL 0x00000003 #define DPORT_PRO_OUT_VECBASE_SEL_S 0 #define PRO_VECBASE_SET (DR_REG_DPORT_BASE + 0x5B0) #define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF #define DPORT_PRO_OUT_VECBASE_REG_S 0 #define APP_VECBASE_CTRL (DR_REG_DPORT_BASE + 0x5B4) #define DPORT_APP_OUT_VECBASE_SEL 0x00000003 #define DPORT_APP_OUT_VECBASE_SEL_S 0 #define APP_VECBASE_SET (DR_REG_DPORT_BASE + 0x5B8) #define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF #define DPORT_APP_OUT_VECBASE_REG_S 0 #define DPORT_REG_DATE (DR_REG_DPORT_BASE + 0xFFC) #define DPORT_DPORT_DATE 0x0FFFFFFF #define DPORT_DPORT_DATE_S 0 #define DPORT_DPORT_DATE_VERSION 0x1605190 #endif /* _SOC_DPORT_REG_H_ */