// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. #include #include "esp_system.h" #include "esp_attr.h" #include "esp_wifi.h" #include "esp_wifi_internal.h" #include "esp_log.h" #include "sdkconfig.h" #include "rom/efuse.h" #include "rom/cache.h" #include "rom/uart.h" #include "soc/dport_reg.h" #include "soc/efuse_reg.h" #include "soc/rtc_cntl_reg.h" #include "soc/timer_group_reg.h" #include "soc/timer_group_struct.h" #include "soc/cpu.h" #include "soc/rtc.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/xtensa_api.h" static const char* TAG = "system_api"; static uint8_t base_mac_addr[6] = { 0 }; void system_init() { } esp_err_t esp_base_mac_addr_set(uint8_t *mac) { if (mac == NULL) { ESP_LOGE(TAG, "Base MAC address is NULL"); abort(); } memcpy(base_mac_addr, mac, 6); return ESP_OK; } esp_err_t esp_base_mac_addr_get(uint8_t *mac) { uint8_t null_mac[6] = {0}; if (memcmp(base_mac_addr, null_mac, 6) == 0) { ESP_LOGI(TAG, "Base MAC address is not set, read default base MAC address from BLK0 of EFUSE"); return ESP_ERR_INVALID_MAC; } memcpy(mac, base_mac_addr, 6); return ESP_OK; } esp_err_t esp_efuse_mac_get_custom(uint8_t *mac) { uint32_t mac_low; uint32_t mac_high; uint8_t efuse_crc; uint8_t calc_crc; uint8_t version = REG_READ(EFUSE_BLK3_RDATA5_REG) >> 24; if (version != 1) { ESP_LOGE(TAG, "Base MAC address from BLK3 of EFUSE version error, version = %d", version); return ESP_ERR_INVALID_VERSION; } mac_low = REG_READ(EFUSE_BLK3_RDATA1_REG); mac_high = REG_READ(EFUSE_BLK3_RDATA0_REG); mac[0] = mac_high >> 8; mac[1] = mac_high >> 16; mac[2] = mac_high >> 24; mac[3] = mac_low; mac[4] = mac_low >> 8; mac[5] = mac_low >> 16; efuse_crc = mac_high; calc_crc = esp_crc8(mac, 6); if (efuse_crc != calc_crc) { ESP_LOGE(TAG, "Base MAC address from BLK3 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc); return ESP_ERR_INVALID_CRC; } return ESP_OK; } esp_err_t esp_efuse_mac_get_default(uint8_t* mac) { uint32_t mac_low; uint32_t mac_high; uint8_t efuse_crc; uint8_t calc_crc; mac_low = REG_READ(EFUSE_BLK0_RDATA1_REG); mac_high = REG_READ(EFUSE_BLK0_RDATA2_REG); mac[0] = mac_high >> 8; mac[1] = mac_high; mac[2] = mac_low >> 24; mac[3] = mac_low >> 16; mac[4] = mac_low >> 8; mac[5] = mac_low; efuse_crc = mac_high >> 16; calc_crc = esp_crc8(mac, 6); if (efuse_crc != calc_crc) { // Small range of MAC addresses are accepted even if CRC is invalid. // These addresses are reserved for Espressif internal use. if ((mac_high & 0xFFFF) == 0x18fe) { if ((mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) { return ESP_OK; } } else { ESP_LOGE(TAG, "Base MAC address from BLK0 of EFUSE CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc); abort(); } } return ESP_OK; } esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__((alias("esp_efuse_mac_get_default"))); esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__((alias("esp_efuse_mac_get_default"))); esp_err_t esp_derive_mac(uint8_t* local_mac, const uint8_t* universal_mac) { uint8_t idx; if (local_mac == NULL || universal_mac == NULL) { ESP_LOGE(TAG, "mac address param is NULL"); return ESP_ERR_INVALID_ARG; } memcpy(local_mac, universal_mac, 6); for (idx = 0; idx < 64; idx++) { local_mac[0] = universal_mac[0] | 0x02; local_mac[0] ^= idx << 2; if (memcmp(local_mac, universal_mac, 6)) { break; } } return ESP_OK; } esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type) { uint8_t efuse_mac[6]; if (mac == NULL) { ESP_LOGE(TAG, "mac address param is NULL"); return ESP_ERR_INVALID_ARG; } if (type < ESP_MAC_WIFI_STA || type > ESP_MAC_ETH) { ESP_LOGE(TAG, "mac type is incorrect"); return ESP_ERR_INVALID_ARG; } _Static_assert(UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR \ || UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR, \ "incorrect NUM_MAC_ADDRESS_FROM_EFUSE value"); if (esp_base_mac_addr_get(efuse_mac) != ESP_OK) { esp_efuse_mac_get_default(efuse_mac); } switch (type) { case ESP_MAC_WIFI_STA: memcpy(mac, efuse_mac, 6); break; case ESP_MAC_WIFI_SOFTAP: if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) { memcpy(mac, efuse_mac, 6); mac[5] += 1; } else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) { esp_derive_mac(mac, efuse_mac); } break; case ESP_MAC_BT: memcpy(mac, efuse_mac, 6); if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) { mac[5] += 2; } else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) { mac[5] += 1; } break; case ESP_MAC_ETH: if (UNIVERSAL_MAC_ADDR_NUM == FOUR_UNIVERSAL_MAC_ADDR) { memcpy(mac, efuse_mac, 6); mac[5] += 3; } else if (UNIVERSAL_MAC_ADDR_NUM == TWO_UNIVERSAL_MAC_ADDR) { efuse_mac[5] += 1; esp_derive_mac(mac, efuse_mac); } break; default: ESP_LOGW(TAG, "incorrect mac type"); break; } return ESP_OK; } void esp_restart_noos() __attribute__ ((noreturn)); void IRAM_ATTR esp_restart(void) { #ifdef CONFIG_WIFI_ENABLED esp_wifi_stop(); #endif // Disable scheduler on this core. vTaskSuspendAll(); esp_restart_noos(); } /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, * triggers restart. */ void IRAM_ATTR esp_restart_noos() { const uint32_t core_id = xPortGetCoreID(); const uint32_t other_core_id = core_id == 0 ? 1 : 0; esp_cpu_stall(other_core_id); // other core is now stalled, can access DPORT registers directly esp_dport_access_int_deinit(); // We need to disable TG0/TG1 watchdogs // First enable RTC watchdog to be on the safe side REG_WRITE(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE); REG_WRITE(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M | (1 << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) | (1 << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) ); REG_WRITE(RTC_CNTL_WDTCONFIG1_REG, 128000); // Disable TG0/TG1 watchdogs TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE; TIMERG0.wdt_config0.en = 0; TIMERG0.wdt_wprotect=0; TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE; TIMERG1.wdt_config0.en = 0; TIMERG1.wdt_wprotect=0; // Disable all interrupts xt_ints_off(0xFFFFFFFF); // Disable cache Cache_Read_Disable(0); Cache_Read_Disable(1); // Flush any data left in UART FIFOs uart_tx_wait_idle(0); uart_tx_wait_idle(1); uart_tx_wait_idle(2); // Reset wifi/bluetooth/ethernet/sdio (bb/mac) DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); // Reset timer/spi/uart DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERS_RST | DPORT_SPI_RST_1 | DPORT_UART_RST); DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Set CPU back to XTAL source, no PLL, same as hard reset rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); // Clear entry point for APP CPU DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); // Reset CPUs if (core_id == 0) { // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST_M | RTC_CNTL_SW_APPCPU_RST_M); } else { // Running on APP CPU: need to reset PRO CPU and unstall it, // then reset APP CPU SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST_M); esp_cpu_unstall(0); SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_APPCPU_RST_M); } while(true) { ; } } void system_restart(void) __attribute__((alias("esp_restart"))); void system_restore(void) { esp_wifi_restore(); } uint32_t esp_get_free_heap_size(void) { return xPortGetFreeHeapSize(); } uint32_t system_get_free_heap_size(void) __attribute__((alias("esp_get_free_heap_size"))); const char* system_get_sdk_version(void) { return "master"; } const char* esp_get_idf_version(void) { return IDF_VER; } static void get_chip_info_esp32(esp_chip_info_t* out_info) { uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG); memset(out_info, 0, sizeof(*out_info)); if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) { out_info->revision = 1; } if ((reg & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) { out_info->cores = 2; } else { out_info->cores = 1; } out_info->features = CHIP_FEATURE_WIFI_BGN; if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) { out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE; } if (((reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S) == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) { out_info->features |= CHIP_FEATURE_EMB_FLASH; } } void esp_chip_info(esp_chip_info_t* out_info) { // Only ESP32 is supported now, in the future call one of the // chip-specific functions based on sdkconfig choice return get_chip_info_esp32(out_info); }