Commit graph

79 commits

Author SHA1 Message Date
Angus Gratton
105c4b7386 Merge branch 'feature/esptool_image_padding' into 'master'
esptool: Optimise app image size by using RAM-loaded data for padding

See merge request !1017
2017-07-19 15:52:22 +08:00
Angus Gratton
2d9770fd00 linker script: Add some comments about significance of 0x18 byte offset 2017-07-19 17:38:05 +10:00
Angus Gratton
c230e4280c linker scripts: Limit DROM/IROM section lengths correctly 2017-07-19 16:33:48 +10:00
Angus Gratton
d92c541b1a esptool: Optimise generated image size by using RAM-loaded data for padding
Can save almost 128KB from some images.
2017-07-19 16:24:17 +10:00
Angus Gratton
f824829a13 Merge branch 'bugfix/dont_link_unused_data_sections' into 'master'
ld: Save RAM by removing unused .data sections at link time

See merge request !985
2017-07-17 14:10:12 +08:00
Angus Gratton
187b5fb888 ld: Remove unused .data sections at link time
Reduces static RAM, code size.
2017-07-12 13:05:54 +08:00
Angus Gratton
71c70cb15c heap: Refactor heap regions/capabilities out of FreeRTOS
Remove tagged heap API, rename caps_xxx to heap_caps_xxx

Also includes additional heap_caps_xxx inspection functions.
2017-07-10 17:46:03 +08:00
Angus Gratton
5ee49fd311 heap: Add new multi_heap heap implementation to replace FreeRTOS-based tagged heaps 2017-07-10 17:46:03 +08:00
Ivan Grokhotkov
9b955f4c9f Merge branch 'feature/sysview_via_apptrace' into 'master'
sysview via apptrace

See merge request !708
2017-06-29 08:40:13 +08:00
Alexey Gerenkov
8d43859b6a esp32: SEGGER SystemView Tracing Support
Implements support for system level traces compatible with SEGGER
SystemView tool on top of ESP32 application tracing module.
That kind of traces can help to analyse program's behaviour.
SystemView can show timeline of tasks/ISRs execution, context switches,
statistics related to the CPUs' load distribution etc.

Also this commit adds useful feature to ESP32 application tracing module:
 - Trace data buffering is implemented to handle temporary peaks of events load
2017-06-27 20:52:43 +03:00
Angus Gratton
b428d28950 spiflash rom: Add symbols accidentally removed in refactor 2017-06-01 09:08:29 +10:00
jack
fc130fba86 fix bug that files missing commit in MR 773 2017-05-31 19:37:39 +08:00
Ivan Grokhotkov
67a147fc6f Merge branch 'bugfix/bt_controller_log_clean_up' into 'master'
component/bt: disable information loggings from bt controller

clean-up information loggings during controller initialization

See merge request !769
2017-05-19 11:50:11 +08:00
wangmengyang
df3164bd58 component/bt: disable information loggings from bt controller 2017-05-18 21:44:06 +08:00
Deomid Ryabkov
a40fd2e7bd esp32.ld: Add an entry for ets_write_char_uart
It is mentioned in ets_sys.h, but not actually PROVIDEd.

Merges https://github.com/espressif/esp-idf/pull/545
2017-05-17 10:45:17 +10:00
Jiang Jiang Jian
1e0710f1b2 Merge branch 'bugfix/bt_acl_tx' into 'master'
components/bt: update libbtdm.a with a bugfix for an assertion failure when ACL-…

…U transmission is resumed

See merge request !755
2017-05-12 18:23:20 +08:00
Jiang Jiang Jian
a6608648db Merge branch 'driver_merge_tmp/mcpwm' into 'master'
feature: Motor Control PWM(mcpwm) driver and examples



See merge request !698
2017-05-12 18:21:38 +08:00
wangmengyang
23965694b1 components/bt: update libbtdm.a with a bugfix for an assertion failure when ACL-U transmission is resumed 2017-05-12 17:53:25 +08:00
Kewal M Shah
2008f4d88c feature: add Motor Control PWM(mcpwm) driver
1. Name change from chopper to carrier, block diagram update, minor changes to example codes
2. mcpwm_reg.h changed, brought uniformity in comments, worked on suggestions, duty to accept float. Some name changes!
3. Minor readme changes and Indetation
4. Minor change:  move mcpwm_reg.h and mcpwm_struct.h to new path
5. Minor change: addition of BLDC example code and Readme
6. Name changed from epwm to mcpwm
7. Improve the reg name in mcpwm_struct.h
8. Name change chopper>carrier, deadband>deadtime
2017-05-12 15:47:59 +08:00
Tian Hao
377a1f5ea1 component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it.
2. fix STALL spelling.
3. check dport access by non-dport access function
2017-05-12 15:41:51 +08:00
wangmengyang
244fbf1e84 component/bt: fix some bugs related to bluetooth sniff mode in controller
1. fix some bugs in bluetooth sniff mode in controller
2. export some symbols to esp32.rom.ld including functions and global variables in ROM code
3. update libbtdm.a which includes "IRAM_ATTR" addition or removal for some functions
2017-05-04 15:08:07 +08:00
XiaXiaotian
9d8425bd72 put RODATA of libphy.a into DRAM
There are some RODATAs of libphy.a that are called in ISR. So need
    to put them into DRAM to avoid access them when R/W SPI flash. Due
    to the RODATAs which are called in ISR haven't been picked out to
    put into DRAM, put all of the RODATA of libphy.a into DRAM. This
    will be optimized in the future.
2017-04-24 11:22:49 +08:00
XiaXiaotian
b238bc691d Do not put the whole object files into IRAM. Add attributes to the functions called in ISR instead. 2017-04-21 15:38:01 +08:00
Alexey Gerenkov
55f1a63faf esp32: Adds functionality for application tracing over JTAG
- Implements application tracing module which allows to send arbitrary
   data to host over JTAG. This feature is useful for analyzing
   program modules behavior, dumping run-time application data etc.
 - Implements printf-like logging functions on top of apptrace module.
   This feature is a kind of semihosted printf functionality with lower
   overhead and impact on system behaviour as compared to standard printf.
2017-04-17 23:26:29 +03:00
Ivan Grokhotkov
15ec487fde Merge branch 'feature/esp32_d2wd_support' into 'master'
ESP32-D2WD support

Support ESP32-D2WD with integrated flash in ESP-IDF.

Includes fix for https://github.com/espressif/esp-idf/issues /521


See merge request !639
2017-04-14 20:57:39 +08:00
Angus Gratton
f7793840e1 bootloader: Add QIO support for ESP32-D2WD SPI flash 2017-04-13 17:55:47 +10:00
Angus Gratton
85e76a7cfc spiflash ROM functions: Remove Quad I/O mode enable/disable code from flash ROM functions
Confusion here is that original ROM has two functions:

* SPIReadModeCnfig() - sets mode, calls enable_qio_mode/disable_qio_mode
* SPIMasterReadModeCnfig() - As above, but doesn't set QIO mode in status register

However we never want to use the ROM method to set/clear QIO mode flag, as not all flash chips work this way. Instead we
do it in flash_qio_mode.c in bootloader.

So in both cases (ROM or "patched ROM") we now call SPIMasterReadModeCnfig(), which is now named
esp_rom_spiflash_config_readmode().
2017-04-13 17:54:42 +10:00
Ivan Grokhotkov
9edab21385 Merge branch 'feature/rtc_clk_impl' into 'master'
Introduce soc component, add source of rtc_clk and rtc_pm libraries

This MR adds parts of the RTC library source code (initialization, clock selection functions, sleep functions). WiFi-related power management functions are kept inside the precompiled library. Most of RTC library APIs have been renamed.

Default CPU frequency option in Kconfig is set to 160MHz, pending qualification of 240MHz mode at high temperatures.

Register header files are moved into the new soc component, which will contain chip-specific header files and low-level non-RTOS-aware APIs (such as rtc_ APIs). Some of the files from ESP32 component were also moved: cpu_util.c, brownout.c, and the corresponding header files. Further refactoring of ESP32 component into more meaningful layers (chip-specific low level functions; chip-specific RTOS aware functions; framework-specific RTOS-related functions) will be done in future MRs.

See merge request !633
2017-04-12 10:38:23 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Alexey Gerenkov
0860f46220 spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
2017-04-11 10:51:19 +08:00
Jiang Jiang Jian
8ee6f8227e Merge branch 'bugfix/reset_mac_cause_bt_cannot_rx_data' into 'master'
Reset WIFI mac when wifi start and update wifi lib

1. reset wifi mac when wifi start

2. roll back rx hung workaround for beacon timeout

3. fix amsdu ap interface wrong issue

4. fix amsdu header parse error

5. fix amsdu flag wrong issue

6. PHY: V350, fix BT rssi bug

7. RTC: V225, fix bt will be not work when wifi is reset

See merge request !606
2017-03-24 17:02:26 +08:00
Ivan Grokhotkov
710c853adc Merge branch 'bugfix/spi_flash_lock_period' into 'master'
SPI flash operations lock for shorter periods

Based on bug report here:
https://esp32.com/viewtopic.php?f=13&t=1489&p=6816#p6773

Long SPI flash erase (and possibly write/read) cycles block all tasks on both CPUs for an extended period, and can lead to WiFi dissassociation (and general priority inversion.)

This MR inserts preemption breaks into large operations (all erases, writes every 8KB, reads every 16KB).

Overhead of a single spi_flash_guart_start()/spi_flash_guard_end() cycle measured at approx 67us (assuming no preemption.)

See merge request !600
2017-03-24 15:55:42 +08:00
Angus Gratton
0e31eb458e esp32: Move heap_alloc_caps to IRAM
Rest of malloc() path was already in IRAM
2017-03-24 10:41:45 +08:00
XiaXiaotian
6181c39f05 Reset WIFI mac when wifi start and update wifi lib
1. reset wifi mac when wifi start

2. roll back rx hung workaround for beacon timeout

3. fix amsdu ap interface wrong issue

4. fix amsdu header parse error

5. fix amsdu flag wrong issue

6. PHY: V350, fix BT rssi bug

7. RTC: V225, fix bt will be not work when wifi is reset
2017-03-23 14:28:27 +08:00
Angus Gratton
6afea0e81c linker scripts: Add explicit symbols for _iram_start and _flash_cache_start
This is to avoid confusion when idf_monitor prints the first symbol in each section, ie "WindowOverflow4" or similar,
when bootloader prints the section mapping address.

Closes #447 https://github.com/espressif/esp-idf/issues/447
2017-03-21 16:45:13 +08:00
Jeroen Domburg
3462b53fbc MR suggestions 2017-03-08 19:27:30 +08:00
Jeroen Domburg
e5f54a9dbd Validate more GPIO ROM functions for non-use of static RAM 2017-03-08 19:04:28 +08:00
Jeroen Domburg
0db8b00b8a tight 28k 2017-03-08 19:04:28 +08:00
Ivan Grokhotkov
848494b20f Merge branch 'feature/enable_qio_directly' into 'master'
Enable SPI flash Quad I/O in bootloader

Bootloader checks flash ID, enables Quad I/O mode based on flash type.

See merge request !479
2017-03-03 11:25:52 +08:00
XiaXiaotian
a51f378ecc bugfix: it causes exception that wifi interrupt happens when read/write flash, if pp_post() is on icache. 2017-02-21 14:25:34 +08:00
XiaXiaotian
eb14284c92 disable PHY and RF when stop WiFi and disable BT
1. Add disable PHY and RF when WiFi and BT are both disabled(including call sniffer disable API).

2. Do not init PHY and RF when cpu start. Init PHY and RF when call Wifi or BT start APIs(including sniffer enable API).

3. Add a temporary lib: librtc_clk.a and will delete it when CPU frequency switching function is done.

4. Add an function to get OS tick rate.

5. Do not put the whole pp.a in iram0, only put lmac.o, ieee80211_misc.o, ets_time.o and wdev.o in iram0.
2017-02-17 10:24:54 +08:00
Angus Gratton
68cba2a1fb Bootloader: Support switching to Quad I/O mode during boot process 2017-02-09 08:44:05 +11:00
Alexey Gerenkov
04acc88023 esp32: Fixes watchdog problem when printing core dump to uart
Also fixes generation of core dumps when flash cache is disabled
2017-02-01 18:39:28 +03:00
Tian Hao
2bb67985dc component/bt : move some codes of controller to iram
1. mv codes which called by sir into iram
2. mv libcoexist.a into iram
2017-01-18 16:38:06 +08:00
Ivan Grokhotkov
9aa0e29079 deep sleep: keep RTC_SLOW_MEM powered on if data is placed into RTC slow memory 2017-01-12 14:15:30 +08:00
Ivan Grokhotkov
e4811216ff deep sleep: fix regression due to moving ets_update_cpu_frequency into IRAM
Deep sleep stub may call ets_update_cpu_frequency, which has been moved from ROM to IRAM.
Restore the ROM version in the linker script, call it ets_update_cpu_frequency_rom, use it in the deep sleep stub.
2017-01-12 14:15:25 +08:00
Ivan Grokhotkov
edd924f273 sdmmc: add peripheral driver and protocol layer 2017-01-09 04:51:24 +08:00
Ivan Grokhotkov
4f909b8ecc Merge branch 'bugfix/ets_delay_on_app_cpu' into 'master'
esp32: ets_update_cpu_frequency should set tick scale for both CPUs

ets_update_cpu_frequency ROM function updates g_ticks_per_us, which is has two copies, one for each CPU.
The APP CPU copy of g_ticks_per_us never got updated, resulting in shorter delays produced by ets_delay_us on the APP CPU.

This MR replaces ROM ets_update_cpu_frequency with a copy in IRAM which updates scaling factors on both of the CPUs.

So now we get expected delays (in microseconds):
```
ets_delay_us core=0 expected=50000 actual=50014
ets_delay_us core=1 expected=50000 actual=50015
vTaskDelay core=0 expected=50000 actual=49428
vTaskDelay core=1 expected=50000 actual=50000
```

Reported on the forum: http://esp32.com/viewtopic.php?f=2&t=713#p3722

See merge request !373
2017-01-07 18:45:14 +08:00
Liu Zhi Fu
a575b9e893 esp32: modify ld file to fix a crash issue 2017-01-07 16:12:07 +08:00
Ivan Grokhotkov
1cbc2fa046 esp32: ets_update_cpu_frequency should set tick scale for both CPUs 2017-01-06 15:00:17 +08:00