components/spi_flash: call SPIUnlock once
This fixes the performance impact for spi_flash_write and spi_flash_erase.
With this change, NVS init in single core mode takes about 50ms (compared to >2seconds before that).
For dual core mode, we still spend on average 2ms for each spi_flash_ operation due to synchronization between CPUs, so NVS startup time is about 2 seconds in dual core mode.
See merge request !80
This fixes the performance impact for spi_flash_write and spi_flash_erase.
With this change, NVS init in single core mode takes about 50ms (compared to >2seconds before that).
Dual core compatible spi flash APIs
Implementation of spi flash APIs which work in dual core mode.
This also includes other changes:
- fixes to FreeRTOS tasks.c made by Jeroen and me — these were originally made to fix issues with high priority tasks seen in WiFi stack, but were required to get stuff in ipc.c working as well
- initial base idea with two high-priority tasks was separated into a separate API — esp_ipc.h. That API allows one to run a function on the other CPU from a high-priority task. Because we don't have preemption across CPUs, this is currently not very fast: it requires on average half a tick until the second CPU switches to the high priority task. Currently that API can be either blocking, or non-blocking with queue length of 1. I haven't yet found a use case for arbitrary sized queue of IPC requests. Anyone who needs that can trivially add that later by replacing a binary semaphore with a generic queue.
With these changes i can run application with WiFi stack and NVS on both cores.
See merge request !25
header files: modify rom code header files and soc header files
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
See merge request !43
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
update ci config file with 2 changes:
1. add build SSC and do sanity test config
2. add tags to each job as sanity test need to be executed on special runner
Test is now only arranged for master branch
See merge request !69
* master: (130 commits)
lwip: Define LWIP_ESP8266 in port lwipopts.h not gcc command line
CI: Build the esp-idf-template with the matching branch name, if it exists
README: Add Resources section with some links
Rename README.buildenv to docs/build_system.rst and ReST-ify it
Eclipse docs: Easier to just replace entire PATH, msys32 has everything we need to build/flash
test_build_system: Print ESP_IDF_TEMPLATE_GIT for easier debugging
Name component makefiles component.mk instead of Makefile
Eclipse doc: Add troubleshooting note about Makefile directories
eclipse_make.sh: Fix printing of make directory
Move bin/eclipse_windows_make.sh to tools/windows_eclipse_make.sh
Eclipse docs: Prepend IDF paths to beginning of PATH
Set default SPI flash access mode to DIO
FreeRTOS: temporary solution for memory canaries and memory debug
tcpip_adapter: fix dhcp client work flow
event: not post got ip event if static is invalid
tcpip_adapter: typedef clean up
event: post got ip event when use static ip
tcpip_adapter: use dhcp callback to post got ip event
dhcp: add dhcp callback
lwip: remove netif_reg_addr_change_cb
...
