While there was no register at DR_REG_FRC_TIMER_BASE + 0x60, due to
peripheral address space wraparound this write actually affected one of
FRC2 registers, which is used by WiFi stack to implement legacy
ets_timer APIs.
This change uses FRC_TIMER_LOAD_REG(0) instead, which can be set to
known value safely.
Organize examples and API documentation - supplement to !430
This supplement to !430, both intended to replace bulky !421.
1. Fixed broken links
2. Added links to available examples in API documentation, where missing
3. Updated links to point directly to example folder (to show README.md with example description)
4. Added README.md in docs folder info to point reader to ReadTheDocs instead of doc sources, ref. https://github.com/espressif/esp-idf/issues/243
5. Fixed some typo errors / Sphinx warnings
6. Fixed memory leak in example, ref. https://github.com/espressif/esp-idf/issues/209
See merge request !440
The block which dispatches ticks on CPU1 was a copy of the code block
for the normal path (CPU0). It used to check uxPendedTicks, with the
logic that uxPendedTicks can be 0 iff the scheduler is not suspended.
On CPU1 however, uxPendedTicks is not related to the state of the
scheduler (as uxPendedTicks is updated on CPU0). Due to this, if CPU0
scheduler was suspended, and uxPendedTicks happened to be nonzero,
tick hooks on CPU1 didn’t run, even though CPU1 scheduler was working.
This change removes the check for uxPendedTicks in CPU1 code path,
so that the tick hooks on CPU1 always get called (as for the CPU0 code
path).
Allow writes to encrypted partitions
There is a size alignment requirement but it is checked by
spi_flash_write_encrypted. However, this check flat-out bans encrypted
writes.
Original PR on Github: https://github.com/espressif/esp-idf/pull/249
See merge request !432
When compiling in release mode, compiler was choosing same register for
oldint and intmask variables, so INTENABLE was never modified.
This effectively broke disabling of non-IRAM interrupts during flash
operations, observed in the existing tests if task watchdog is enabled.
This change adds an extra constraint tells the compiler that output
operand should not be placed into the same register as an input one.
Parse unit test cases from test files
As of now, we need to sync three different places when adding new unit test cases. The plan is to add a python script in tools/unit-test-app. This script would parse unit test cases from the C files with tests and generate the needed YAML files in components/idf_test/unit_test. CI would run this script in build stage to create the files and unit-test stage would use the generated files to run tests.
To get the needed test metadata, we need to add some more tags in the test case functions. For example:
```
TEST_CASE("SYS_LIB_0102 test time functions", "[stdlib][fails][env=UT_T1_APC]")
{
//...
}
```
Reason for this kind of implementation is that we need the YAML files for generating documents.
See merge request !275
Add python script that parses list of unit test cases for CI from component test folder
Modify .gitlab-ci.yml to run this script as part of build unit tests stage
spi_flash_enable_interrupts_caches_and_other_cpu function used to enable
non-IRAM interrupts after giving up flash operation lock, which would
cause problems if another task was waiting on the lock to start a flash
operation. In fact, non-IRAM interrupts should be re-enabled before the
task scheduler is resumed. Otherwise non-pinned task can be moved to the
other CPU due to preemption, causing esp_intr_noniram_enable to be
called on the other CPU, causing an abort to be triggered.
Fixes the issue reported in
https://github.com/espressif/esp-idf/pull/258
Delete option to select core timer 2 as a FreeRTOS tick source
Core timer 2 is unusable for FreeRTOS ticks because it triggers a high-level interrupt. This MR deletes the option to select it.
Ref https://github.com/espressif/esp-idf/issues/234
See merge request !418
In some cases (when RTC register reads are performed from the APP CPU), a write to FRC_TIMER_INT_REG may be lost on the bus.
Writing to another DPORT register immediately before or after that works around the issue.
We write one dummy value to an address which doesn’t have any register associated with it.
Fixes https://github.com/espressif/arduino-esp32/issues/120
1. add openssl option at menuconfig
2. remove SSL_ERR to reduce complexity
3. add more functions about debugging and assert
According these, our coders and customers may use and debug the OpenSSL code easily.
