newlib: fix register used for DPORT/RTC bug workaround
While there was no register at DR_REG_FRC_TIMER_BASE + 0x60, due to
peripheral address space wraparound this write actually affected one of
FRC2 registers, which is used by WiFi stack to implement legacy
ets_timer APIs.
This change uses FRC_TIMER_LOAD_REG(0) instead, which can be set to
known value safely.
See merge request !449
fixes for issues observed when using spi_flash
This MR fixes three unrelated issues:
- Race condition in spi_flash_enable_interrupts_caches_and_other_cpu
when operations on unpinned tasks are performed.
The issue is reported in https://github.com/espressif/esp-idf/pull/258
- esp_intr_noniram_disable doesn’t disable interrupts when compiled in
release mode. This issue manifested itself with an illegal instruction
exception when task WDT ISR was called at the time when flash was
disabled.
Fixes https://github.com/espressif/esp-idf/issues/263.
- Tick hooks on CPU1 were not called if CPU0 scheduler was disabled for
significant amount of time (which could happen when doing flash erase).
The issue manifested itself as “INT WDT timeout on core 1” error.
Fixes https://github.com/espressif/esp-idf/issues/219.
See merge request !441
While there was no register at DR_REG_FRC_TIMER_BASE + 0x60, due to
peripheral address space wraparound this write actually affected one of
FRC2 registers, which is used by WiFi stack to implement legacy
ets_timer APIs.
This change uses FRC_TIMER_LOAD_REG(0) instead, which can be set to
known value safely.
The block which dispatches ticks on CPU1 was a copy of the code block
for the normal path (CPU0). It used to check uxPendedTicks, with the
logic that uxPendedTicks can be 0 iff the scheduler is not suspended.
On CPU1 however, uxPendedTicks is not related to the state of the
scheduler (as uxPendedTicks is updated on CPU0). Due to this, if CPU0
scheduler was suspended, and uxPendedTicks happened to be nonzero,
tick hooks on CPU1 didn’t run, even though CPU1 scheduler was working.
This change removes the check for uxPendedTicks in CPU1 code path,
so that the tick hooks on CPU1 always get called (as for the CPU0 code
path).
Allow writes to encrypted partitions
There is a size alignment requirement but it is checked by
spi_flash_write_encrypted. However, this check flat-out bans encrypted
writes.
Original PR on Github: https://github.com/espressif/esp-idf/pull/249
See merge request !432
When compiling in release mode, compiler was choosing same register for
oldint and intmask variables, so INTENABLE was never modified.
This effectively broke disabling of non-IRAM interrupts during flash
operations, observed in the existing tests if task watchdog is enabled.
This change adds an extra constraint tells the compiler that output
operand should not be placed into the same register as an input one.
Add python script that parses list of unit test cases for CI from component test folder
Modify .gitlab-ci.yml to run this script as part of build unit tests stage
spi_flash_enable_interrupts_caches_and_other_cpu function used to enable
non-IRAM interrupts after giving up flash operation lock, which would
cause problems if another task was waiting on the lock to start a flash
operation. In fact, non-IRAM interrupts should be re-enabled before the
task scheduler is resumed. Otherwise non-pinned task can be moved to the
other CPU due to preemption, causing esp_intr_noniram_enable to be
called on the other CPU, causing an abort to be triggered.
Fixes the issue reported in
https://github.com/espressif/esp-idf/pull/258
Delete option to select core timer 2 as a FreeRTOS tick source
Core timer 2 is unusable for FreeRTOS ticks because it triggers a high-level interrupt. This MR deletes the option to select it.
Ref https://github.com/espressif/esp-idf/issues/234
See merge request !418
In some cases (when RTC register reads are performed from the APP CPU), a write to FRC_TIMER_INT_REG may be lost on the bus.
Writing to another DPORT register immediately before or after that works around the issue.
We write one dummy value to an address which doesn’t have any register associated with it.
Fixes https://github.com/espressif/arduino-esp32/issues/120
One common pattern of using assert function looks as follows:
int ret = do_foo();
assert(ret == 0); // which reads as: “do_foo should never fail here, by design”
The problem with such code is that if ‘assert’ is removed by the preprocessor in release build,
variable ret is no longer used, and the compiler issues a warning about this.
Changing assert definition in the way done here make the variable used, from language syntax perspective.
Semantically, the variable is still unused at run time (as sizeof can be evaluated at compile time), so the compiler
can optimize things away if possible.
These functions are marked as inline and are called from functions which are in IRAM.
In release (-Os) builds, the compiler may decide not to inline these functions.
Placing these functions into IRAM explicitly works around this.
update wifi lib: fix some wifi lib bugs
1. net80211: fix get ap info error(a4614877)
2. tw9358: sta mac same with softap(ea38d32c)
3. tw9221: scan channel error when connected(183d469c)
See merge request !425
bootloader_random_disable: Restore all SARADC/I2S registers to defaults
Fix for issue with I2S0 not being usable after bootloader_random_enable()
See merge request !415
fixes for github issues
This MR includes commits from several Github PRs, as well some fixes for issues reported on Github and on the forum.
- compile PHY-related code only when WiFi is enabled
- fix macOS setup instructions
- fix some of the Sphinx warnings
- update docs index, improve structure of the readme-
- wifi: fix typos, rename ESP_ERR_WIFI_NOT_START to ESP_ERR_WIFI_NOT_STARTED
- sdmmc: fix explanation of flash voltage regulator configuration efuses
- sdmmc: change idx num of example
- fix i2c_get_period name
- fix esp_log_level_set function name in docs
See merge request !420
If using WIFI_INIT_CONFIG_DEFAULT, error message will point out lack
of WiFi. Otherwise linker errors on WiFi symbols should help give a
clue as to what is broken.
Piggy-backs on changes in !420, ref github #230#237
Fix panic register dump format
Fix misplaced a printf somewhere causing an enter to be printed after every register in the panic regdump instead of every 4th register.
Fixes https://github.com/espressif/esp-idf/issues/236
See merge request !419
esp32 core dump to flash
1. menuconfig option to select where to store core dump: flash, uart or disable
2. Saving of core dump to flash
3. Partition table definitions files with core dump partition
4. Python scripts to support core dump generation from GDB command line
See merge request !341
The following issues mentioned during MR!341 review were fixed:
1) Core dump test application description
2) Usage of CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH and CONFIG_ESP32_ENABLE_COREDUMP_TO_UART
3) FLASH_GUARD_START macro usage is fixed in flash API
4) Core dump module logging facility
5) cache util functions doc updated
6) interactive delay before print core dump to uart
7) core dump partion support in build system
component bt:Added the create attribute table method to the new API
GATT Server service table APIs.
Have already modify the style and other things as @jeroen suggestion in other MR(the MR have been closed)
See merge request !399
