Commit graph

7 commits

Author SHA1 Message Date
Angus Gratton
be53a6950c spi_flash_erase_range: Allow for 32KB blocks not 64KB blocks
SPI flash hardware sends 52h command, which is a 32KB erase.

There is a matching bug in the ROM SPIEraseArea code, unless
flashchip->block_size is modified first.
2016-11-24 18:05:06 +11:00
Ivan Grokhotkov
42827ff869 bootloader, menuconfig: add flash size setting support 2016-10-21 15:27:25 +11:00
Angus Gratton
feca308f1f rom/spi_flash.h: Remove first parameter of SPI_read_status_high()
Corrects the prototype to match the one compiled into ROM.
2016-10-21 10:44:05 +11:00
Wangjialin
41d397cf3f Only modify headers in soc/ .
Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
2016-09-14 13:47:28 +08:00
Wu Jian Gang
04b53643ef header files: clean up
1. format;
2. Slow RTC memory reverse 2KB;
2016-09-12 17:47:50 +08:00
jack
24011ddd05 header files: modify rom code and soc header files
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
2016-09-12 17:47:49 +08:00
Ivan Grokhotkov
bd6ea4393c Initial public version 2016-08-17 23:08:22 +08:00