Commit graph

211 commits

Author SHA1 Message Date
Ivan Grokhotkov
3323f31cfb soc: implement XTAL frequency detection
ROM code already implements XTAL frequency detection, but it uses the 8M
clock before the clock tuning parameters are initialized. With the
zero clock tuning parameter, 8M clock has significant frequency deviation
at high temperatures, which can lead to erroneous detection of 40 MHz
crystal as a 26 MHz one.

This change adds XTAL frequency detection code to rtc_clk_init routine,
and detection is performed after the 8M clock tuning parameter as been
initialized.
2017-04-24 15:29:30 +08:00
Alexey Gerenkov
77a92e6dcc esp32: Added dumping info from traceport upon reset by any WDT
- Last PC info and waiti mode indication are printed for both CPUs
 - Raw traceport regs values are printed only for log levels higher than DEBUG
2017-04-23 22:07:56 +03:00
Ivan Grokhotkov
404e89da4d Merge branch 'bugfix/rtc_reg_fields' into 'master'
soc: allow REG_SET_FIELD to be used for bit fields

- Fixes an issue with `rtc_clk_apll_enable`: https://esp32.com/viewtopic.php?f=13&t=1673
- Fixes `rtc_clk_fast_freq_set` function always selecting XTAL/4 as fast clock source.
- Fixes regression in deep sleep current (7uA instead of 5uA).

See merge request !674
2017-04-21 19:40:45 +08:00
Ivan Grokhotkov
6e9d60ef70 rtc_clk_init: handle case when XTAL frequency has already been set
On first reset, ROM code writes the estimated XTAL frequency into
RTC_APB_FREQ_REG (aka STORE5). If the application doesn’t specify exact
XTAL frequency (which is always the case for now), rtc_clk_init will
guess what kind of XTAL is used (26M or 40M), based on the estimated
frequency. Later, detected frequency is written into RTC_XTAL_FREQ_REG
(aka STORE4).

When the application switches clock source to PLL, APB frequency changes
and RTC_APB_FREQ_REG is updated. If the application encounters an RTC
WDT reset, RTC_APB_FREQ_REG will not be updated prior to reset. Once the
application starts up again, it will attempt to auto-detect XTAL
frequency based on RTC_APB_FREQ_REG, which now has value of 80000000.
This will fail, and rtc_clk_xtal_freq_estimate will fall back to the
default value of 26 MHz. Due to an incorrect XTAL frequency, PLL
initialization will also take incorrect path, and PLL will run at a
different frequency. Depending on the application this may cause just
garbage output on UART or a crash (if WiFi is used).
2017-04-21 10:33:58 +08:00
Ivan Grokhotkov
5d1bb42c18 soc: allow REG_SET_FIELD to be used with single-bit fields 2017-04-18 17:34:26 +08:00
Ivan Grokhotkov
faaf59ccb3 soc: define missing M, V macros for nrx, bb, fe, emac, iomux
Recipe:
- Add _M and _V for single-bit fields
  Search: (#define (\w+)\s*(\(BIT\(\d+\)\)))
  Replace: \1\n#define \2_M \3\n#define \2_V 1

- Add _M and _V for multi-bit fields
  Search: (#define (\w+)\s*(0x[\dA-Fa-f]+))
  Replace: \1\n#define \2_M (\2_V << \2_S)\n#define \2_V \3
2017-04-18 17:34:26 +08:00
Jeroen Domburg
0b79d07d34 add detection of invalid cache access
- fix level 4 interrupt vectors to produce correct backtrace
- initialize invalid cache access interrupt on startup
- handle invalid cache access in panic handler
2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
3c6c1e36ec soc: add invalid cache access interrupt bits to dport_reg 2017-04-13 15:27:38 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Ivan Grokhotkov
9ff446e6f9 soc: convert line endings to unix 2017-04-11 15:44:22 +08:00
Ivan Grokhotkov
d6dbf15a1f soc: move header files into soc component 2017-04-11 14:06:40 +08:00