This fixes a bug introduced by !848, where APP CPU would not be reset
during esp_restart, if esp_restart was called from a task running on APP
CPU, and wouldn’t be reset by PRO CPU on startup.
This change replaces stalling APP CPU with resetting it.
Also adds a non-automated esp_restart tests.
DPORT access protection can not work when the other CPU is stalled.
Writes to DPORT registers in esp_restart caused the program to hang due
to access protection, and the reset happened due to RTC_WDT, not SW_RST.
This change adds esp_dport_access_int_deinit function and calls it from
esp_restart once the other core is stalled.
In ESP32 rev. 0, switching between 240MHz and 80MHz (even via an
intermediate frequency of 40MHz) may cause the chip to lock up.
The bootloader used to enable 80MHz CPU clock at startup, which could
cause lock up after software reset. With this change, if 240MHz CPU
clock is enabled in menuconfig, bootloader will also use 240MHz to avoid
lock-up.
Run some unit test cases based (poorly) around sodium's test infrastructure.
Increase in unity test task stack is due to signature tests, load a lot of data onto the stack.
- Fix slave initiate service discovery procedure
- Fix master re-discovery every time connection established
- Optimize service discovery char ccc write procedure
- Optimize esp_log_buffer function
- Modify default supervision timeout from 20s to 2s
This seems to clean up some of the more wrong addr2line output results (not
sure why, something to do with optimisations I think - perhaps the return
address may also be a jump target from some earlier line of the code.)
Previously, this resulted in task stack frames turning up incorrectly in the backtrace, ie
Backtrace: 0x400d22a0:0x3ffb0fa0 0x40085a3c:0x3ffb0fc0 0x400f32c4:0x3ffb0fe0 0x40081965:0x3ffb1010
0x400d22a0: esp_vApplicationIdleHook at /home/esp/esp-idf/components/esp32/./freertos_hooks.c:
52
0x40085a3c: prvIdleTask at /home/esp/esp-idf/components/freertos/./tasks.c:4431
0x400f32c4: i2c_isr_handler_default at /home/esp/esp-idf/components/driver/./i2c.c:598
0x40081965: _xt_lowint1 at xtensa_vectors.o:?
Fix is to implement abort() via an unhandled exception rather than a breakpoint, I think
because of relative priority of exception types.
Another approach would be to assign a software-only INUM to abort()ing and defined a
PANIC_RSN_ABORTED, but this is more complex and interrupt numbers are more scarce than RAM!
When ‘reset halt’ command is executed, OpenOCD will take the APP CPU
out of reset and enable the clock. At this point, user can set a
breakpoint on code which will run on APP CPU. Previously, app startup
code would do another reset of APP CPU, thereby removing any breakpoints
which may have been set. This change makes APP CPU reset conditional on
DPORT_APPCPU_CLKGATE_EN bit, which is 0 by default but is set to 1 by
OpenOCD after reset.
